| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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10180328-209D Price Single chip solution for improved system integration Supports cell level transfer mode Meets 50MHz performance offering up t0 400Mbps cell rate transfers Cell and clock rate decoupling with on chip FIFOs Up t0 1.5 KByte of on chip FIFO per data direction Integrated management interface and built-in errored cell discard ATM Cell size programmable via external pins from 16 t0 128 bytes Optional Utopia parity generation/checking enable/disable via external pin Built in JTAG port (IEEE1149 compliant) Simulation model available for system level verification (Contact Quicklogic for details) 10180328-209D on stock Infineon Technologies AG . Fiber Optics ' Wernerwerkdamm 16 . Berlin D-13623, Germany Infineon Technologies, Inc. * Fiber Optics . 19000 Homestead Road . Cupertino, CA 95014 USA Siemens K.K. . Fiber Optics . Takanawa Park Tower ' 20-14, Higashi-Gotanda, 3-chome, Shinagawa-ku * Toky0 141, Japan NOTES ISample tested at +25IC to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% t0 90% of +5 V) and timed from a voltage level of +1.6 V. 2See Figures 6, 7 and 8. 3Refer to the Standby Mode Operation section. The MAX specification of l ccs is valid when using a 0.1 decoupling capacitor on the VREF pin. 4Measured with the load circuit of Figure l and defined as the time required for an output to cross 0.8 V or 2.4 V. 'These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure l. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice. |
