| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| 1N3882JANTX | microsemi | 04+ | 11 |
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1N3882JANTX Datasheet
1N3882JANTX Price A low level on the synchronous parallel enable input, SPE, disables counting operation and allows data at the PO to P3 inputs to be loaded into the counter (provided that the setup and hold requirements for SPE are met). 1N3882JANTX on stock REFERENCE INPUT 115v @ 1.2 ma rms 400 Hz (LDS 504-HJ (Transformer Isolated> 26V @ 5 ma rms 400 Hz (LDS 5041) DYNAM C RESPONSE: For a +900 Step input, 5 ms to rated accuracy
NOTES: 1. All VDD pins must be connected t0 3.3V power supply. 2. All VDOO pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (OV). 3. All Vss pins must be connected to ground supply. 4. Package body is approximately 14mm x 20mm x l.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign these pins as Vss. Customers who plan to take advantage of the upgrade path should treat these pins as VSS on the 70V3379 and 70V3389. If no upgrade is needed, the pins can be treated as NC. |
