MOTMap-1330  > 1N5382B
description ZENER DIODE 140V 5% 5.0W T-18
Technical/Catalog Information 1N5382B
Vendor Microsemi
Category Discrete Semiconductor Products
RoHS Status RoHS Non-Compliant
Other Names 1N5382B 1N5382B 1N5382BMSTR ND 1N5382BMSTRND 1N5382BMSTR
Lead Free Status Contains Lead
Mounting Type Through Hole, Axial
Packaging Tape & Reel (TR)
Operating Temperature -65掳C ~ 150掳C
Package / Case T-18, Axial
Tolerance 卤5%
Power - Max 5W
Voltage - Forward (Vf) (Max) @ If 1.2V @ 1A
Current - Reverse Leakage @ Vr 500nA @ 101V
Voltage - Zener (Vz) (Nom) 140V @ 8mA
Impedance (Zzt) (Max) @ Izt 230 Ohm @ 8mA

suppliers of 1N5382B and PDF data of 1N5382B

Part Numbert Mfg Packt D/C Descriptiont Qty Company/Contact  
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1N5382B Datasheet
Mitsubishi Electric Europe B.V. Semiconductor Travellers Lane, Hatfield Hertfordshire, AL10 8XB, England Email: semis.info@meuk.mee.com Phone: +44-1707-278-900 Fax: +44-1707-278-837
1N5382B Price

Pin unction Description Interface Schematic
10 RF OUT Amplifier RF output. This is an unmatched collector output of the final amplifier transistor. It is internally connected to pins 1 0, 11, 13, and 14 to provide low series inductance and flexibility in output matching. Bias for the final power amplifier output transistor must also be provided through two of these four pins. Typically, pins 10 and 11 are connected to a network that creates a second harmonic trap. For 830MHz opera- tion, this network is simply a single 2.4 pF capacitor from both pins to ground. This capacitor series resonates with internal bond wires at two times the operating frequency, effectively shorting out the second har- monic. Shorting out this harmonic serves to increase the amplifier's maximum output power and efficiency, as well as to lower the level of the second harmonic output. Typically, pins 13 and 14 are externally connected very close to the package and used as the RF output with a matching network that presents the optimum load impedance to the PA for maximum power and efficiency, as well as providing DC blocking at the output. An additional network of a bias inductor and parallel resistor provides DC bias and helps to protect the output from high voltage swings due to severe load mismatches. Shunt protection diodes are included to clip peak voltage excursions above approximately 15V to prevent voltage breakdown in worst case conditions.
11 RF OUT Same as pin 10.
12 GND Same as pin 4
13 RF OUT Same as pin 10.
14 RF OUT Same as pin 10.
15 NC Not internally connected.
16 NC Not internally connected.
Pkg Base GND This contact is the main ground contact for the entire device. Care should be taken to ensure that this contact is well soldered in order to prevent performance from being degraded from that indicated in the specifications.


MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the main memory to either buffer l or buffer 2. An 8-bit opcode, 53H for buffer l and 55H for buffer 2, is followed by the five reserved bits, 10 address bits (PA9-PAO) which specify the page in main memory that is to be transferred, and nine don't care bits. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don't care bits from the Sl pin. The transfer of the page of data from the main memory to the buer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (tXFR), the status register can be read to determine whether the transfer has been completed or not.