| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| 2N36 | MOT | 06+ | 3900 |
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| 2N36 | MOT | PLS BID | 04+ | 2560 |
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| 2N36 | MOT | CAN | 2560 |
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| 2N36 | MOT | CAN | In stock | 3900 |
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| 2N36 | MOT | CAN | STRC Verified | 2560 |
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| 2N36 | MOT | CAN | STRC Verified | 2560 |
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2N36 Datasheet 1 Reverse battery voltage is allowed only with external input and status resistors to limit the currents to a safe value. 2 For normal continuous operation. A higher Ti is allowed as an overload condition but at the threshold Tj00) the over temperature trip operates to protect the switch. 3 0f the output Power MOS transistor. 2N36 on stock Copyright@ 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. GigaPHY is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies whereas th e MT4LC 16M4T8 refresh es one row for every C BR cycle. So with eit her device, executin g 4,096 C BR cycles covers all ro w s. Th e CBR refresh will in voke the internal refresh counter for automatic RAS# address- in g. Altern atively, RAS#-ONLY REFRESH capability is in h eren tly pro vid ed. However, with this m eth od only on e row is refresh ed at a tim e; so for the MT4LC 16M4A7, 8,192 RAS#-ONLY REFRESH cycles must be executed every 64m s to cover all row s. So m e com patibilit y issues may become apparent. JEDEC strongly recommends the u se of CBR REFRESH for this device. An option al selfrefresh m ode is also available on th e "S" version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LO W for th e specified tRASS. Th e " S" option allo w s for an extended refresh period of 128m s, or 31.25 hts per row for a 4K refresh and 15.625Us per row for an 8K refresh, when using a distributed CBR REFRESH. This refresh rate can be applied durin g no rm al operatio n , as well as durin g a stan dby or battery backup mode. Th e selfrefre sh m ode is term in ated by drivin g RAS# HIG H fo r a m mim um tim e oftRP S. This delay allo w s fo r the com pletio n of an y in tern al refresh cycles th at m ay be in process at the time of the RAS# LOW-to-HIGH tran sition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exitin g self refresh . However, if the DRAM con - troller utilizes RAS#-ONLY or burst CBR refresh se- quen ce, all rows m u st be refresh ed within th e average in tern al refre sh rate p rio r to th e re sumption ofn orm al operation.
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