85201-1402 Datasheet Fast charging is accomplished by the low "ON" resistance MOSFET, Q1. The application microprocessor is able to "Pulse Charge" the battery via the MAINCHARGEREN control input of Si9731. The processor monitors the battery voltage via the system ND converter and varies the pulse charging duty cycle accordingly to maintain fast charging. Note that even though charging current may be sufficiently high, pulse charging with short "ON" time and long "OFF" time ensures that heat generation due to thermal heating is reduced. 85201-1402 on stock| VCE(sat, lC = 10 A; VGE = 15 V; TVJ = 250C TVJ = 1250C | 2.3 2.7 | 2.7 V V | | VGE(th, IC = 0.4 rTiA; VGE = VCE 4.5 | | 6.5 V | | ICES VCE= VCES; VGE = 0 V; TVJ = 25aC TVJ = 1250C | O6 | 0.6 mA mA | | IGES VCE = 0 V; VGE = + 20 V | | 200 nA | | td(on, t Inductive loa t:(off) V;k? g I250' tf VCE = 600 V; E VGE = +15 V; | 50 40 290 60 1.2 1 .1 | ns ns ns ns mJ mJ | | C. VCE = 25 V; VGE = O V; f =1 MHz Qe:. VCE= 600V; VGE = 15 V; lc = 10 A | 600 45 | pF nC | | RthjC (per IGBT) | | 1.2 K/W | | | |
| Rectifier Fail Alarm (RFA) Equalize Occurring (EQO) High Voltage Occurring (HVO) Temporary Restraint Occurring (TRO) Thermal Shutdown Occurring (THSD) Open Sense Lead Has Occurred (OS) Low Current Alarm LCA) AC Power Has Failed Alarm ACF) Rectifier Fan Has Failed Alarm (FF) DC Breaker Is Open Alarm DCBKR) AC Breaker Is Open Alarm ACBKR) Note: All alarms are "Form A" relay type contacts | High Voltage Shutdown (HVSD) Allcontrolinputs Restart (RS) areinitiatedwith Equalize (EQ) agroundclosure Temporary Release (TR) 24VAC voltage Emergency Shutdown (EMSD) reference to ground | | Page 2 | RM4850 4/98 REV A | | |
General Description The ACT-F512K8 is a high speed, 4 megabit CMOS monolithic Flash module designed for full temperature range military, space, or high reliability applications. This device is input TTL and output CMOS compatible. The command register is written by bringing WE to a logic low level (VIL), while CE is low and OE is at logic high level (VIH). Reading is accomplished by chip Enable (CE) and Output Enable (OE) being logically active, see Figure 9. Access time grades of 60ns, 70ns, 90ns, 120ns and 150ns maximum are standard.
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