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NOTES 'Temperature range is as follows: Y Version: -40YC ro +105YC. 2A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest. 3Recalibration at any temperature will remove these drift errors. 4Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. 5Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. oGain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error-Unipolar Offset Error for unipolar ranges and Full-Scale Error-Bipolar Zero Error for bipolar ranges. 7Gain Error Drifr does not include Unipolar Ojet Drift/Bipolar Zero Drift. It is ectively the drift of the part if zero-scale calibrarions only were performed as is the case with background calibration 8These numbers are guaranteed by design and/or characrerization. gThe common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. loThe input volrage range on the analog inputs is given here with respect to the voltage on the respective negative input ofits differential or pseudo-differential pair. See Table VII for which inputs form differential pairs. "VREF = REF IN(+) - REF IN(-). 12These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load. '3Sample tested at +25YC to ensure compliance. 14See Burnout Current section. 15After calibration, if the input voltage exceeds positive full scale, the converter will output all ls. If the input is less than negative full scale, then the device outputs all Os. 16These calibrarion and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND - 30 mV. The offset calibration limit applies to borh the unipolar zero point and the bipolar zero point. 17For higher gains (>8) at fCLKIN = 2.4576 MHz, the BST bit of the Filter High Register must be set t0 1. For other conditions, it can be set to O. isWhen using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on the crystal or resonator type (see Clocking and Oscillator Circuit section). 19Measured at de and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz. 20PSRR depends on gain.