JAN2N552 Datasheet General Layout Considerations Due to the high switching frequency and high transient currents produced by the device, careful board layout is a must.A clean board layout using a ground plane and short connections to all capacitors will improve noise perfor- mance and ensure proper regulation. JAN2N552 Price| j | | | i 20ms | | | j | | | | | | fl ser'e | s | | | | | | ~ | | | | | | | | j | | | | | | | | | | | | | | | |
JAN2N552 on stock| Parameter | Symbol | Conditions | MIN | TYP | MAX | Unit | | Collector to emitter voltage | VCEO(SUS) | le = 4.0 A, lB = 0.4 A, L = 1 mH | 60 | | | V | | Collector to emitter voltage | VCEX(SUS) | le = 4.0 A, IBl = -IB2 = 0.4 A, VBE(OFF) = -1.5 V, L = 180 LtH, clamped | 60 | | | V | | Collector cutoff current | ICBO | VCB = 60 V, IE = 0 | | | 10 | A | | Collector cutoff current | ICER | VCE = 60 V, RBE = 50 Q, Ta =1250C | | | 1.0 | mA | | Collector cutoff current | ICEX1 | VCE = 60 V, VBE(OFF) = -1.5 V | | | 10 | LtA | | Collector cutoff current | ICEX2 | VCE = 60 V, VBE(OFF) = -1.5 V, Ta = 1250C | | | 1O | mA | | Emitter cutoff current | IEBO | VEB = 5.0 V, le = 0 | | | 10 | A | | DC current gain | hFEl* | VCE = 2.0 V, le = 0.7 A | 100 | | | | | DC current gain | hFE2* | VCE = 2.0 V, le = 1.5 A | 100 | 200 | 400 | | | DC current gain | hFE3* | VCE = 2.0 V, le = 4.0 A | 60 | | | | | Collector saturation voltage | VCE(sal)l* | le = 4.0 A, lB = 0.2 A | | | O3 | V | | Collector saturation voltage | VCE(sal)2* | lc = 6.0 A, IB = 0.3 A | | | 0.5 | v | | Base saturation voltage | VBE(sat)l* | le = 4.0 A, lB = 0.2 A | | | 1.2 | V | | Base saturation voltage | VBE(sat)2* | le = 6.0 A, lB = 0.3 A | | | 1.5 | V | | Collector capacitance | Cob | VCB = 10 V, IE = O, f = 1.0 MHz | | 100 | | pF | | Gain bandwidth product | fT | VCE =10 V, le = 1.0 A | | 150 | | MHz | | Furn-on time | ton | le = 4.0 A, RL = 12.5 Q, | | O1 | 0.3 | vs | | Storage time | tstg | IBi = -lB2 = 0.2 A, Vcc 50 V Refer to the test circuit. | | 1.0 | 1.5 | vs | | Fall time | tf | | O1 | 0.3 | /1S | | | | | | | |
The bus Master begins a transmission by sending a START condition. The Masterthen sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 0101 for the CAT5259 (see Figure 5). The next four significant bits (A3, A2, A1, AO) are the device address bits and define which device the Masteris accessing. Up to sixteen devices may be individually addressed by the system. Typically, +5V and ground are hard-wired to these pins to establish the device's address. | Symbol | Parameter | Value | Unit | | | Ambient Operating Temperature (3) | -40 t0 125 | | | l BIAS | Temperature Under Bias | -50 t0 125 | | | l STG | Storage Temperature | -65 t0 150 | | | Vl0(2) | Input or Output Voltage (except A9) | -2 t0 7 | V | | Vcc | Supply Voltage | -2 t0 7 | V | | VA9(2) | A9 Voltage | -2 t0 13.5 | V | | VPP | Program Supply Voltage | -2 t0 14 | V | | | | |
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