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KPSA56-123(V2) Datasheet O The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. KPSA56-123(V2) Price
KPSA56-123(V2) on stock also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (l/00 through l/Ois) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from l/0 pins (l/00 through l/O-r), is written into the location specified on the address pins (Ao through Ais). If Byte High Enable (BHE) is LOW, then data from l/0 pins (l/08 through l/Ois) is written into the location specified on the address pins (Ao through Ais). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on l/00 to l/07. If Byte High Enable (BHE) is LOW, then data from memory will appear on l/08 to l/Ois. See the truth table at the back of this data sheet for a complete description of read and write modes.
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