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KPY63AK Datasheet

I Description The LH5081 is a 280 PIO fabricated with CMOS silicon gate process technology and is com- patible with the conventional 280 NMOS PIO (LH0081) Due to the CMOS static structure. it provides low power consumption and large operating margin. The power save mode can be obtained with a software control on the models suffixed with "L".
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			Speed Bins
Parameter List		Symbol	55ns		70ns		100ns		Units
Parameter List		Symbol	Min	Max	Min	Max	Min	Max	Units
Read	Read cycle time	tRC	55		70		100		ns
	Address access time	tAA		55		70		100	ns
	Chip select to output	tC01tC02		55		70		100	ns
	Output enable to valid output	tOE		25		35		50	ns
	Chip select to low-Z output	tLZl,tL22	10		10		10		ns
	Output enable to low-Z output	tOLZ	5		5		5		ns
	Chip disable to high-Z output	tHZl,tH22	0	20	0	25	0	30	ns
	Output disable to high-Z output	tOHZ	0	20	0	25	0	30	ns
	Output hold from address change	tOH	10		10		10		ns
Write	Write cycle time	twC	55		70		100		ns
	Chip select to end of write	tCw	45		60		80		ns
	Address set-up time	tAS	0		0		0		ns
	Address valid to end of write	tAW	45		60		80		ns
	Write pulse width	tWP	40		50		60		ns
	Write recovery time	tWR	0		0		0		ns
	Write to output high-Z	tWHZ	0	20	0	25	0	30	ns
	Data to write time overlap	tDW	25		30		40		ns
	Data hold from write time	tDH	0		0		0		ns
	End write to output low-Z	tOw	5		5		5		ns

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BOOTSTRAPPED FIGURE 2 III

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Cl	select input capacitance	Conditions		2.5		pF
CS	switch capacitance	OFF-state		6.0		pF
CS	switch capacitance	ON-state		18		pF

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