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Notes: 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1Wns), timing reference levels of VCC(typ /2, input pulse levels of o to VCC(typ ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 11. At any given temperature and voltage condition, tHZCE iS less than tLZCE, tHZOE iS less than tLZOE, and tHZWE iS less than tLZWE for any given device. 12. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CEl = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write
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