M51953AFP-C61J Price| IVIN | VCC Supply Current | VIN = 5V (Below UVLO) Vlw = 8V, 200ffA Pull-Up on VBAT (4.5V) No Bat VIN = 8V, VBAT = 2.5V Trickle Vlw = 8V, VBAT = 3.5V Charge | q q q | 1 5 12 1.0 1.4 2.0 10 17 21 0.5 3.0 5.0 | mA mA mA | | VLKOH | Viw Undervoltage Lockout High | | q | 5.5 6.5 7.5 | V | | VLKOL | Viw Undervoltage Lockout Low | | q | 5.0 6.0 7.0 | V | | IVBAT | VBAT Current | VIN = 5V (Below UVLO), VBAT = 4.2V VIN = 8V, VBAT = 4.25V No Bat VIN = 8V, VBAT = 2.5V Trickle Vlw = 8V, VBAT = 3.5V Charge | q q q | -1 - 0.1 1 40 73 120 -19 -16 -9.5 -2.7 -1.3 -0.5 | ccA mA mA | | VCLAMP | VBAT Clarrip | No Bat (External 200ffA Pull-Up on VBAT) | q | 4.25 4.5 475 | V | | VMAX | High VBAT Threshold | High Going Threshold Low Going Threshold | q q | 4.25 4.51 4.75 4.25 4.50 4.75 | V V | | VMIN | Low VBAT Threshold | High Going Threshold Low Going Threshold | q q | 2.55 2.7 2.85 2.45 2.6 2.75 | V V | | ISENSE | SENSE Pin Current | Charge State, VSENSE = 3V | q | 85 100 115 | | | VC10 | SENSE Pin C/10 0ffset | Charge State, Vcio = (VBAT - VSENSE) | q | ±1 ±2.5 | mV | | | | | | |
M51953AFP-C61J on stock Dual I2C Interfaces - Interchip bus interface for EEPROMs, LCD controllers, A/D converters, keypads - Master and slave modes, support for multiple masters - Automatic interrupt generation with programmable level System debug support - Real-time instruction trace for determining dynamic execution path - Background debug mode (BDM) for debug features while halted - Debug exception processing capability - Real-time debug support System Interface - Glueless bus interface and DRAMC support for interface t0 16-bit for DRAM, SRAM, ROM, FLASH, and I/O devices - Two programmable chip-select signals for static memories or peripherals with programmable wait states and port sizes. - Two dedicated chip selects for 16-bit wide DRAM/SDRAM. CSO is active after reset to provide boot-up from external FLASH/ROM. - Two dedicated chip selects (CS2 and CS3) are used for the IDE and/or SmartMedia interface - Programmable interrupt controller (low interrupt latency, eight external interrupt requests, programmable autovector generator) - 44 programmable general-purpose inputs (for the 160 MAPBGA package) - 46 programmable general-purpose outputs (for the 160 MAPBGA package) - IEEE 1149.1 Test (JTAG) Module Clocking | Pin No | Pin Name | Io | Description | | 1 | VINP | I | Non-inverting input of the differential input buffer. Internally biased. | | 2 | VINM | l | Inverting input of the differential input buffer. Internally biased. | | 3 | vss | | Ground | | 4 | CLK | l | 3.58MHz TTL Clock input pin. | | 5 | FSKO | O | FSK demodulator output. Delivers the digital data during the FSKO demodulation. Logic low when inactive. | | 6 | PD | l | Power Down active high | | 7 | VDD | | VDD | | 8 | VCOM | | Reference voltage pin. Connect O.lyF Capacitor to VSS. | | | | |
Vertical power DMOS switch Low on-state resistance 5 V logic compatible input Overtemperature protection - self resets with hysteresis Overload protection against short circuit load with output current limiting; latched - reset by input High supply voltage load protection Supply undervoltage lock out Status indication for overload protection activated Diagnostic status indication of open circuit load Very low quiescent current Voltage clamping for turn off of inductive loads ESD protection on all pins Reverse battery and overvoltage protection
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