| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| MC74LS166DR2 | ON | 09/10+ | 9800 |
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| MC74LS166DR2 | ON | SOP-16 | 06+ | New original packing | 130 |
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| MC74LS166DR2 | MOT | 3.9mm 16 | 04+ | 2016 |
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MC74LS166DR2 Datasheet 3.597 3.201 2.809 2.423 2.140 1.936 1.783 1.651 1.488 1.397 1.299 1.240 1.194 1.101 1.045 0.979 0.924 0.925 0.890 0.885 MC74LS166DR2 Price In the low data rate mode, the interval tPRI between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the first RF amplifier is set by a resistor RPR be- tween the PRATE pin and ground. The interval can be adjusted be- tween 0.1 and 5 Us with a resistor in the range of 51 K t0 2000 K. The value of the RPR is given by: MC74LS166DR2 on stock o o o o . n < . J o r n < v ~ d d - a o u e y . e d a o a s e ' E 1 0 1 0 l o a l l o j - a o u m o e d e : ) a s e a a l J a l l ! c u ] T he AD 905 7's encode input is T T L/C M OS compatible and the 8-bit digital outputs can be operated from +5 V or +3 V supplies. A power-down function may be exercised to bring total con- sumption to < 10 mW. In power-down mode the digital outputs are driven to a high impedance state. Following the start condition, the X24165 monitors the SDA bus comparing the slave address being transmitted with its slave address device type identifier. Upon a correct compare the X24165 0utputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24165 will execute a read or write operation. |
