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N74F113D623 Datasheet

Parameter 150U(R).. U nits Conditions
Tj Max.junction operating temperature range -40 t0 180
Tstg Max. storage temperature range -40 t0 180 ac
RmjC Max.thermalresistance,junction to case 0 3 DC operation
Rtrics Max.thermal resistance, case to heatsink 0 1 K/W Mounting surface, smooth, flat and greased
T Max. allowed mounting torq ue +0 -20% 17 Nm Notlubricated threads
14 5 Lubricated threads
wt Approximate weight 130 g
Case style D0-205 (D0-8) See Outline Table


N74F113D623 Price

ltem Symbol Condition Unit
DC Input Voltage VDS <10 v
Channel Temperature Tcri 145 oc
Forward Gate Current lgsf <19.4 mA
Reverse Gate Current lgsr >-2.0 mA
Gate Resistance Rg 100 Q


N74F113D623 on stock

Min Typ Max
Collector-Base cutoff current - Kollektorreststrom IE = 0, VCB = 32 V ICBO IE = 0, VCB = 32 V, Ti = lOOoC ICBO 100 nA 10 [.r,A
Emitter-Base cutoff current - Emitterreststrom Ic = 0, VEB = 5 V IEBO 100 nA
Collector saturation volt. - Kollektor-Sattigungsspg. 2) IC = 10 mA,IB = 0.5 mA VCEsat Ic = 50 mA,IB = 5 mA VCEsat 120 mV 210 mV 250 mV


Parameter Temp Test Level Min Typ Max Unit
SERIAL PORT CLOCK TIMING REQUIREMENTS tSCLK SCLK Period tSCLKL SCLK Low Time tSCLKH SCLK High Time Full Full Full IV IV IV 10.0 1.60 0.5 x tSCLK 1.60 0.5 x tSCLK ns ns ns
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0) tssi SDI to .1-SCLK Setup Time tHSI SDI to .I,SCLK Hold Time tsscs SCS to TSCLK Setup Time tHSCS S~S to TSCLK Hold Time tD5DO TSCLK to SDO Delay Time Full Full Full Full Full IV IV IV IV IV 1.30 0.40 4.12 -2.78 4.28 7.96 ns ns ns ns ns
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1) tssi SDI to .I,SCLK Setup Time tHSI SDI to .1-SCLK Hold Time t55RF5 SRFS to .1,SCLK Setup Time tHSRFS SRFS to .l-SCLK Hold Time tSSTFS STFS to TSCLK Setup Time tH5TFS STFS to TSCLK Hold Time tsscs SCSto TSCLK Setup Time tHSCS S~S to TSCLK Hold Time tDSDO TSCLK to SDO Delay Time Full Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV IV 0.80 0.40 1.60 -0.13 1.60 -0.30 4.12 -2.76 4.29 7.95 ns ns ns ns ns ns ns ns ns