| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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N74F1804N602 Price +15k V ESD Protection As with all Maxim devices, electrostatic discharge (ESD) protection structures are incorporated on all pins to protect against ESD encountered during handling and assembly. The MAX1406 driver outputs and receiv- er inputs have extra protection against static electricity found in normal operation. Maxim's engineers devel- oped state-of-the-art structures to protect these pins against +15kV ESD without damage. After an ESD event, the MAX1406 continues working without latchup. N74F1804N602 on stock Note 5: Vcc = 3V, fSAMPLE = 200kHz, tr = tf = 5ns unless otherwise specified. Note 6: Guaranteed by design, not subject to test. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing th rough the actual endpoints of the transfer cu rve. The deviation is measured from the center of the quantization band. Note 8: The rising edge of CONV starts a conversion. If CONV returns low at a bit decision point during the conversion, it can create small errors. For best performance, ensure that CONV returns low either within 120ns after the conversion starts (i.e., before the first bit decision) or after the 14 clock cycles. (Figure 13 Timing Diagram). Data Inputs/Outputs (DQ8-DQ14). The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ1 5A-1 Low will select the LSB of the Word on the other addresses, DQ1 5A-1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address In- puts to include this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Com- mand Interface. |
