| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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N74F3038D602 Datasheet DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. N74F3038D602 Price These devices consist of a 32-bit shift register, 32 latches, and control logic to enable outputs. HVOUTl is connected to the first stage of the shift registerthrough the Output Enable logic. Data is shifted th rough the shift register on the low to hig h transition of the clock. The HV94 shifts in the counterclockwise direction when viewed from the top of the package and the HV93 shifts in the clockwise direction. A data output buffer is provided for cascading devices. This output reflects the cu rrent status of the last bit of the shift register (32). Operation of the shift register is not affected by the LE (latch enable) or the OE (output enable) inputs. Transfer of datafrom theshift registerto the latch occurs when the LE input is high. The data in the latch is retained when LE is low. N74F3038D602 on stock The PLL can be power controlled in two ways. The first method is by setting the CE pin LOW. This asynchronously powers down the PLL and TRI-STATEs the charge pump output, regardless of the PWDN bit status. The second method is by programming through MICROWIRE, while keeping the CE HIGH. Programming the PWDN bit in the N register HIGH (CE = HIGH) will disable the N counter and de-bias the fIN input (to a high impedance state). The R counter functionality also becomes disabled. The reference oscillator block powers down when the power down bit is asserted. The OSCIN pin reverts to a high impedance state when this condition exists. Power down forces the charge pump and phase comparatorlogic to a TRI-STATE condition. A power down counter reset function resets both N and R counters. Upon powering up the N counter resumes count- ing in "close" alignment with the R counter (the maximum error is one prescaler cycle). The MICROWIRE control reg- ister remains active and capable of loading and latching in data during all of the power down modes.
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