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N74F545N602 N74F545N602 N74F545N602 Datasheet

SRAM read Cycle 2, the Chip Enable - Controlled Access in figure 3b,ls initiated by En going active while G remains asserted, Wn remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV iS satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0).
N74F545N602 N74F545N602 N74F545N602 Price

BGA	SIGNAL	DESCRIPTION	OUTPUT DRIVE
H2	COLO
H1	COL1
J4	COL2
J3	COL3
J2	COL4	Keyboard Interface	8 mA
J1	COL5
K4	COL6
K2	COL7
B1	TCLK	JTAG Clock. This signal should be pulled-up to VDD
B2	TDO	JTAG Data Out	4 mA
C1	TMST	JTAG Test Mode Select. This signal should be pulled-up to VDD
C3	MEDCHG	Media Change for Smart Card interface
D1	BATOK	Battery OK
D2	nBATCHG	Battery Change
G1	KMIDAT	Keyboard / Mouse data	16 mA
H3	KMICLK	Keyboard /Mouse clock	16 mA
L9	BUZ	Buzzer Output (254 kHz MAX.)	8 mA
AB7	nBLE2	Byte Lane Enable 2	16 mA
Y8	nBLE1	Byte Lane Enable 1	16 mA
AA12	BATCNTL	Battery Control for /VD controller battery monitor.	16 mA
N11	BOOTWIDTHO	Boot Width Pins. Used with the MEDCHG bit. On power up, the values on these pins are
N12	BOOTWIDTH1	latched to determine the width and type of Boot device. Boot width can be 8-, 16-, or 32-bit.
W12	LR YM	Touch Screen Controller Lower Right Y-minus
AA13	AN1	A/D channel 1
Y13	AN6	A/D channel 6
W13	LL YP	Touch Screen Controller Lower Left Y-plus
AB14	AN5	A/D channel5
AA14	AN2	A/D channel 2
Y14	UR XM	Touch Screen Controller Upper Right X-minus
W14	AN4	A/D channel4
AB15	AN3	A/D channel3
Y15	UL XP	Touch Screen Controller Upper Left X-plus,
W16	nTESTO	Test Pins. Tie to VDD.
Y17	nTEST1	Test Pins. Tie to VDD.
AA22	OSCEN	Oscillator Enable Output	8 mA
C18	nCAS	Column Address Strobe Signal	16 mA
D17	nRAS	Row Address Strobe Signal	16 mA
A15	nBLE3	Byte Lane Enable 3	8 mA
B15	nBLEO	Byte Lane Enable 0	8 mA
C15	DQMO
D15	DQM1
A14	DQM2	Data Mask for synchronous memories	16 mA
B14	DQM3	Data Mask for synchronous memories	16 mA
B13	sc¨O	Smart Card Interface l/0	16 mA
C13	SCICLK	Smart Card Interface Clock	16 mA
D13	SCIRESET	Smart Card Interface Reset	16 mA
A12	SCIVCCEN	Smart Card Interface VCC Enable	16 mA

N74F545N602 N74F545N602 N74F545N602 on stock


p	High	2.0	2.8	3.6	V
(CTL-A/BC1	Low	0		0.5	V

Characteristic	Sym	Notes	Minimum	Typical	Maximum	Units
Center Frequency at 250C Absolute Frequency	fc	1.2	916 400	916 500	916 600	MHz
Tolerance from 916.500 MHz	AfC	1.2			±100	kHz
Insertion Loss	\|L	1		4	5	dB
3 dB Bandwidth	BW	1,2	600	750	1000	kHz
Rejection at fc - 21.4 MHz (Image)			33	40
at fc - 10.7 MHz (LO)		1	15	37		dB
Ultimate		1		80		dB
Temperature Operating Case Temp.	Tc		-40		+85	oC
Turnover Temperature	To			25		oC
Turnover Frequency	fo	3.4		fc		MHz
Freq. Temp. Coefficient	FTC	3.4		0 032		pp rri/o C
Frequency Aging Absolute Value during the First Year	lfAI	5		<10		ppm/yr
External Impedance Series Inductance	L	1	Coilcraft 8.2 nH Chip		nductor	nH
Shunt Capacitance	c	1	1		5	pF
Lid Symbolization (in addition to Lot and/or Date Codes)	RF			RF1181

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