N74F760D-T Datasheet| SYMBOL | PARAMETER | MIN | TYP | MAX | UNITS | TEST CONDITIONS | | Gps | Common Source Power Gain | 10 | | | dB | ldq = 0.80 A, Vds = 28.0 V, F = 1,OOOMHz | | 11 | Drain Efficiency | | 40 | | % | ldq = 0.80 A, Vds = 28.0 V, F = 1,000 MHz | | VSWR | Load Mismatch Tolerance | | | 20:1 | Relative | ldq = 0.80 A, Vds = 28.0 V, F =1,OOOMHz | | | | | | | |
N74F760D-T Price| Parameter | Symbol | Conditions | Min | Typ | Max | Unit | | Collector-base voltage (Emitter open) | VCBO | IC = -10 IiA. IE = 0 | -20 | | | V | | Collector-emitter voltage (Base open) | VCEO | IC = -1 mA.IB = 0 | -18 | | | V | | Emitter-base voltage (Collector open) | VEBO | IE = -10 yA,Ic = 0 | -5 | | | V | | Collector-base cutoff current (Emitter open) | ICBO | VCB = -10 V, IE = 0 | | | -1 | LLA | | Collector-emitter cutoff current (Base open) | ICEO | VCE = -18 V,IB = O | | | -10 | LLA | | Forward current transfer ratio | hFEl 4 | VCE = -2 V, IC = -500 mA | 130 | | 280 | | | hFE2 | VCE = -2 V, IC = -1.5 A | 50 | | | | Collector-emitter saturation voltage | VCE(sat) | IC = -1 A,IB = -50 mA | | | - 0.5 | V | | Base-emitter saturation voltage | VBE(sat) | Ic = -500 mA, IB = -50 mA | | | -1.2 | V | | Transition frequency | fT | VCB = -6 V,IE = 50 mA, f= 200 MHz | | 200 | | MHz | | Collector output capacitance (Common base, input open circuited) | Cob | VCB = -6 V, IE = 0, f'= 1 MHz | | 40 | | pF | | | | | | | |
N74F760D-T on stock Sometimes at starting or during data receiving, some bit data group (composed of sixteen consecutive signal waves belonging to the same frequency band) may be affected by interference noise, this causing the number of its waves to vary and the consequent synchronous discrepancy between "RXDT-" and "RXCK" signals. To correct this discrepancy, the sixteenth dividing counter of frequency incorporated in this RF-module IC for "RXCK" clock signal generation are always reset at the moment at which any internal demodulated bit data changes from "0" to "1" so that "RXCK" terminal signals are forcibly output at L-level with the timing shown below. This correction is made automatically regardless of whether or not receiving signals are properly input. (The frequency dividing counter is not reset at bit data change from "1" to "0".) | | | | | | | | | | | | | | | | f=l~dHz | | | | | | | | | vcs = ov | | | | | | | | | | | | | | | | | | | | | | | | | | | jL | cl" | | | | | | | | | | | | | | | | | | | | l | | | | | C rss | | | | | f | | C l | I | l | | | | | | | | | | | | | |
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