In the Xilinx XCR3128, the four mandatory JTAG pins each require a unique, dedicated pin on the device. However, if JTAG and ISP are not desired in the end-application, these pins may instead be used as additional general l/0 pins. The decision as to whether these pins are used for JTAG/ISP or as general l/0 is made when the JEDEC file is generated. If the use of JTAG/ISP is selected, the dedi- cated pins are not available for general purpose use. How-
N74F821D N74F821D N74F821D on stock| (2.0 +0 02) 22 +0.4 22 +0.4 _i | |
| | (0.87 +0.016) | (0.87 +0.016) | |
| I ooo 345 Bottom view 1 2 | J o N n | I 11 (o C. |
| | J ' | J | J - 1 | I |
| | 15 +0.4 | | 3.4 +0.4 |
| | | | | | |
| Parameter | Symbol | Min. | Typ | Max. | Unit |
| Power supply voltage | Vcc | 4.5 | 5 0 | 5 5 | V |
| | | | | |
