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N74F821D-T N74F821D-T N74F821DT Datasheet

l Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max 1 62.5 oC/w oC/w


N74F821D-T N74F821D-T N74F821DT Price
Chip select. When CSO and CSl are HIGH and ~S2 is LOW, these three inputs select the UART. When any of these inputs are inactive, the UART remains inactive (refer to AS description). Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (CTS) of the modem status register indicates that CTS has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. This pin has no effect on the UART's transmit or receive operation.
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Parameter Symbol Condition Min Typ Max Units
OUTA, OUTB (Cont.)
Ripple Rejection PSRR f = 120Hz, CBYP = 10nF 60 dB
Output Voltage Noise en f = 10Hz t0 99kHz, IOUT = 50mA, CBYP = 10nF, Cour = 2.2pF 50 hiVRMS
BYP
Start-up Rise Time tr CBYP=10nF 1.5 ms
ENABLE (ENA, ENB)
Enable Input Threshold VIH 1.6 V
VIL 0.4
Enable Input Current IEN 0.2 IJA
RSTA, RSTB
Reset Threshold VTH VOUT falling 88 90 92 %VOUT
VOUT rising 90 92 94
Reset A Delay tRSTA 30 50 70 ms
Reset B Delay tRSTB VDLYB=OV 90 1 50 210 ms
Reset A. B Output Voltage''' VOH ISOURCE = 0.5mA 80 %VOUT
VOL ISINK = 1.2mA 0.3 V
DLYB
Delay Voltage Threshold VDLYB 1.225 1.250 1.275 V
Delay Source Current IDLYB VOUTB< VTH 2.1 3.0 3.9 UA
OVER TEMPERATURE PROTECTION
High Trip Level TH, 1 50 IC
Hysteresis THYST 20 ][c


INVA INVB (Pins 4, 13): Inverting Input. ~ch of theINV pins is an inverting input of an op amp. Note that the INV pins are high impedance, sensitive nodes of the filter and very susceptible to coupling of unintended signals. Capacitance on the INV nodes will also affect the fre- quency response of thefilter sections. R)r these reasons, printed circuit connectionsto theINV pins must be kept as short as possible.