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N74F826D N74F826D N74F826D Datasheet

INPUTS				OUTPUTS		OPERATING
SD	RD	CP	D	Q		MODE
L	H	x	x	H	L	Asynchronous set
H	L	x	x	L	H	Asynchronous reset
L	L	x	x	H	H	Undetermined*
H	H	1	h	H	L	Load1
H	H	1	l	L	H	Load "0"
H	H		x	NC	NC	Hold

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Parameters	12CWQ...	Units	Conditions
IF(AV, Max.AverageForward (PerLeg) Current*SeeFig.5 (PerDevice)	6 12	A	50%duty cycle @Te =1350C,rectangularwaveform
IFSM Max.PeakOneCycleNon-Repetitive	320	A	5ps Sineor3psRect.pulse	Following:any rated '..
SurgeCurrent (PerLeg)'SeeFig.7	130	A	10msSineor6msRect.pulse	load condition and with rated VRRM applied
EAS Non-Rep.AvalancheEnergy(PerLeg)	10	mJ	Tj=250C,IAS=2.OAmps,L=5mH
IAR RepetitiveAvalancheCurrent (PerLeg)	2.0	A	Curre nt decaying linearlyto zero in l psec Frequencylimited by Tj max. VA = 1.5 xVR typical

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This document contains information on a product under development at Advanced Micro Devices The information is intended to help you evaluate this product AMD reserves the right to change or discontinue work on this proposed nrnrliirf^,l+hnlif nn+iro	Publication# 20794 Rev: A Amendment/0 Issue Date: March 1996

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			1 1
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	A= +850C ÷			_7nor			j	L
!	[YPICAL VDROPOUT LIMIT							-
IIIIII - POWER-LtMAX PACKAGE OPE REGION AT TJ(MAX) = +1500c							lATII	UG