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N74LS107-SIG-SMD-DN Datasheet

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0.8 VDS max \
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N74LS107-SIG-SMD-DN Price

Relay type 41.31 4I.52, 41.61
Screw terminal socket: panel or 35 mm rail (EN 50022) mount BLUE 95.03 95.05
BLACK* 95.03.0 95.03O
Identification tag 095.00.4 095.00.4
Modules 99.02 99.02
Timer modules 86.10, 86.20 86.10, 86.20
8-way jumper link for 95.03 and 95.05 sockets 095.18 095.18


N74LS107-SIG-SMD-DN on stock

Orderoode Input voltage Output voltage Output current max. Effiaenqc typ.
1HP 3-2411 THP 3-2412 1HP 3-2422 1HP 3-2423 9 -40 VDC 5 VDC 12 VDC +12 VDC +15 VDC 600 mA 250 mA +125 mA +100 mA 78 % 83 % 83 % 83 %
1HP 3-4811 1HP 3-4812 THP 3-4822 'THP 3-4823 18 -80 VDC 5 VDC 12 VDC +12 VDC +15 VDC 600 mA 250 mA +125 mA +100 mA 78 % 83 % 83 % 83 %
1HP 3-7211 1HP 3-7212 fHP 3-7222 THP 3-7223 36 -160 VDC 5 VDC 12 VDC +12 VDC +15 VDC 600 mA 250 mA +125 mA +100 mA 78 % 83 % 83 % 83 %


-75 -85 -90 -10
PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT
Cycle Time tCYC 8 5 10 10 12 ns
Clock Access Time tCD 7 5 8 5 9 0 10 ns
Output Enable to Data Valid tOE 3.5 3 5 3 5 3.5 ns
Clock High to Output Low-Z tLZC 2 5 2 5 2 5 2.5 ns
Output Hold from Clock High tOH 2 5 2 5 2 5 2.5 ns
Output Enable Low to Output Low-Z tLZOE O 0 O O ns
Output Enable High to Output High-Z tHZOE 3 5 3 5 3 5 4.0 ns
Clock High to Output High-Z tHZC 4 0 5 0 5 0 6.0 ns
Clock High Pulse Width tCH 2 5 3 0 3 0 3.0 ns
Clock Low Pulse Width tCL 2 5 3 0 3 0 3.0 ns
Address Setup to Clock High tAS 2 0 2 0 2 0 2.0 ns
Address Status Setup to Clock High tss 2 0 2 0 2 0 2.0 ns
Data Setup to Clock High tDS 2 0 2 0 2 0 2.0 ns
Write Setup to Clock High (GW, BW, WEx) tws 2 0 2 0 2 0 2.0 ns
Address Advance Setup to Clock High tADVS 2 0 2 0 2 0 2.0 ns
Chip Select Setup to Clock High tcss 2.0 2 0 2 0 2.0 ns
Address Hold from Clock High tAH 0 5 0 5 0 5 0.5 ns
Address Status Hold from Clock High tSH 0 5 0 5 0 5 0.5 ns
Data Hold from Clock High tDH O5 0 5 0 5 0.5 ns
Write Hold from Clock High (GW, BW, WEx) tWH 0 5 0 5 0 5 0.5 ns
Address Advance Hold from Clock High tADVH 0 5 0 5 0 5 0.5 ns
Chip Select Hold from Clock High tCSH 0 5 0 5 0 5 0.5 ns
ZZ High to Power Down tPDS 2 2 2 2 cycle
ZZ Low to Power Up tPUS 2 2 2 2 cycle


 
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