| Symbol | Type | Function |
| CK, CK' | Input | The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ's and DM's that are sampled on both edges of the DQS. |
| CKE | Input | Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. |
| CS | Input | CS enables the command decoder when low and disabled the com- mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. |
| RAS | Input | Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. |
| CAS | Input | Latches column addresses on the positive going edge of the CK with ~AS low. Enables column access. |
| WE | Input | Enables write operation and row precharge. Latches data in starting from AS, WE active. |
| DQS | Input/Output | Data input and output are synchronized with both edge of DQS. |
| DMoDM3 | Input | Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DMo for DQo ~ DQ7, DMi for DQ8 ~ DQis, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. |
| DQoDQ31 | Input/Output | Data inputs/Outputs are multiplexed on the same pins. |
| BAo, BAi | Input | Selects which bank is to be active. |
| AoAii | Input | Row/Column addresses are multiplexed on the same pins. Row addresses : RAo ~ RAii, Column addresses : CAo ~ CA7. Column address CA8 is used for auto precharge. |
| VDDNss | Power Supply | Power and ground for the input buffers and core logic. |
| VDDQNssQ | Power Supply | Isolated power supply and ground for the output buffers to provide improved noise immunity. |
| VREF | Power Supply | Reference voltage for inputs, used for SSTL interface. |
| MCL | Must Connect Low | Must connect Low |
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