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N80930-AD4 Datasheet

Parameter		Symbol	Test Conditions	VG26(V)(S)18165C				Unit	Notes
				-5		-6
				Min	Max	Min	Max
Operating current		lccl	RAS cycling LCAS / UCAS cycling tRC = rTiiri		120		1 10	mA	1.2
	Low power S-version		TTL interface RAS, LCAS / U~AS = VIH Dout = High-Z		2		2	mA
Standby	Low power S-version	ICC2	CMOS interface RAS,CAS > Vcc -0.2V Dout = High-Z		0.25		0.25	mA
Current	Standard power version		TTL interface RAS,LCAS / U~AS = VIH Dout = High-Z		2		2	mA
Current	Standard power version		CMOS interface RAS, CAS > Vcc -0.2V Dout = High-Z		1		1	mA
RAS-only refresh current		lCC3	RAS cycling, LCAS/UCAS = VIH tRC = miri		120		1 10	mA	1.2
EDO page mode current		ICC4	tRC= rriiri		90		80	mA	1.3
CAS-before-RAS refresh current		lcc5	tRC = rTiiri RAS, LCAS / U~AS cycling		120		1 10	mA	1.2
Self-refresh current (S - Version)		ICC8	tRAS100pr,s		350		350	A
CAS- before- RAS long refresh current (S-Version)		lCC9	Standby: Vcc-0.2V RAS ~AS before RAS refresh: 2048 cycles / 128ms RAS,LCAS / UCAS: OV .< VIL < 0.2V VCC-0.2ViVIHiVIH (Max) Dout = High-Z, tRAS < 300ns		500		500	A

N80930-AD4 Price

PARAMETER	TEST CONDITIONS	MIN TYP MAX	UNIT
Start threshold voltage		10 3	v
Stop threshold voltage		7.5	V
Vhys Hysteresis voltage		1 1.5	V
tpd Propagation delay time	50-mV overdrive, See Note 2	300 1000	ns
td Falling-edge delay time	See Note 2	2 5	us

N80930-AD4 on stock

The term IADJ X R2 represents the error added by the adjust pin current. Ri is chosen so that the mimmum load current is at least lOmA. Ri and R2 should be of the same composi- tion for best tracking over temperature. The divider resis- tors should be placed physically as close to the load as pos- sible.

Ao FO Fi	-J -	^1 A2P cTv2V2 Vcci F3 F2 ^3S3 S2 5 VEE S1 50
F2 F3 vcci VCC2 COUT P G qN	CERAHIC DJP	S2 A3E E '2 ~ VEE ^0 F0 83Ul G B3i	FLAT PACK	83qN J B2Bo 81VEE Bo B E CIN s A3	PLCC	F1 F A VEE A1 42
B2 ro So B1	B0

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