The CN8330 is an integral DS3/E3 framer designed to support the transmission formats defined by ANSI Tl.107-1988, T1.107a-1989, T1.404, and ITU-T G.751 standards. All ma ntenance features required by Bellcore TR-TSY-000009 and AT&T PUB 54014 are provided. In addition, the CN8330 can be optionally configured as a High-Level Data Link Controller (HDLC) usable with or without DS3/E3 framing overhead. The CN8330 provides framing recovery for M13, Gbit parity, Stntran, and G751 E3 formatted signals. A First In First Out (FIFO) buffer in the receive path can be enabled to reducejitter on the incoming data. Transmit and receive data is available to the host in either serial or parallel byte and nibble formats. Access is provided to the terminal data link and the Par Bid AlarrrVControl (FEAC) channel, as specified in T1.107a-1989. Counters are included for frame-bit errors, Line Code Violations (LCVs), parity errors, and Par Bid Block Brors (FEs). Two operational modes are available: microprocessor and stand-alone monitor control modes. The microprocessor control mode monitors all status conditions and provides configuration control. The stand-alone monitor mode allows the CN8330 to operate as a monitor providing status and alarm information on external pins.
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N80960SA-1692 on stock| Diode capacitance VR = 1 V, f =l MHz | CT | | 0.35 | 0.6 | pF |
| Case capacitance f=lMHz | CC | | 0.09 | |
| Differential resistance VR=O,f=lOkHz | Ro | | 225 | | kl |
| Series inductance chip to ground | Ls | | 0.6 | | nH |
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| 1JJb 11.4 (13.5) | | |
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