| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
N80C186L Datasheet
N80C186L Price When the IDLE n instruction is used, it slows the processor's internal clock and thus its response time to incoming interrupts the l-cycle response time ofthe standard IDLE state is in- creased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21xx will remain in the IDLE state for up to a maximum ofn CLKIN cycles (where n = 16, 32, 64, or 128) before resuming normal operation. N80C186L on stock Monitoring voltages: 5V t0 9V Independent core voltage monitor Triple voltage detection and reset assertion -Standard reset threshold settings. See selec- tion table on page 2. -Adjust low voltage reset threshold voltages using special programming sequence -Reset signal valid to Vcc = 1V -Monitor three separate voltages Fault detection register Selectable power-on reset timeout (0.05s, 0.2s, 0.4s, 0.8s) Selectable watchdog timer interval (25ms, 200ms, 1.4s or off) Debounced manual reset input Low power CMOS -25pA typical standby current, watchdog on -6pA typical standby current, watchdog off Memory security 4Kbits of EEPROM -16 byte page write mode -5ms write cycle time (typical) Built-in inadvertent write protection -Power-up/power-down protection circuitry -Block lock protect 0, or l/2, of EEPROM 400kHz 2-wire interface 2.7V t0 5.5V power supply operation Available packages -14-lead SOIC, TSSOP
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