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N823YB Datasheet

The standard ACT-F128K8 0ffers access times between 60ns and 150ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls. The ACT-F128K8 is command set compatible with JEDEC standard l Mbit EEPROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the
N823YB Price

SYMBOL	PARAMETER	CONDITIONS	TYP	MAX	UNIT
Rtr, j-nib Rtr, j-a	Thermal resistance junction to mounting base Thermal resistance junction to ambient	in free air	60	0.65	K/W K/W

N823YB on stock

			Ratings
Parameter	Symbol	Conditions	mi¨n	typ	max	U nit
		During drive operation (CT = low, ST = low)		6 5	9 1	mA
Current drain	lcc	During lock protection (CT = high, ST = low)		2 2	3 1	mA
Current drain	lcc	Standby mode (ST = high)		110	150	UA
Lock detection capacitor charge current	ICT1		1 9	2 8	3 7	UA
Capacitor discharge current	ICT2		0 32	046	0 60	UA
Capacitor charge/discharge current ratio	RCT	RCD = ICTl/ICT2	5.0	6 0	7 0
CT charge voltage	VCT1		2 55	2 75	2 95	V
CT discharge voltage	VCT2		1 6	1 8	2 0	V
Output low-level voltage	VOL	10= 200 mA		0 2	0 3	V
Output high-level voltage	VOH	In= 200 mA	3.9	4 1		V
Hall input sensitivity	VHN	Zero peak value (Including the offset and hysteresis.)		7	15	mV
RD output pin low-level voltage	VRD	IRD=5mA		0 1	0 3	V
RD output pin leakage current	IRDL	VRD= 15V			30	UA
HB output low-level voltage	VHBL	IHB=5mA		1 0	1 3	V
ST pin input current	IST	VST= 5V		75	100	UA

					IIIII 60CKQ045
					RthjC (DC) = 0.420C/W



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