| | | Version | | |
| Parameter | Symbol | ·80 | ·1H | -1L | Unit | Note |
| Row active to row active delay | tRRD( rTiin) | 16 | 19 | 19 | ns | 1 |
| RAS to ~AS delay | tRCD( rTiin) | 19 | 19 | 24 | ns | 1 |
| Row precharge time | tRP(min) | 19 | 19 | 24 | ns | 1 |
| | tRAs(rriin) | 48 | 50 | 60 | ns | 1 |
| Row active time | tRAs(max) | 100 | us | |
| Row cycle time | tRc(Fliin) | 67 | 69 | 84 | ns | 1 |
| Last data in to row precharge | tRDL(ITiin) | 2 | CLK | 2 |
| Last data in to Active delay | tDAL(Friin) | tRDL+ tRP | | 3 |
| Last data in to new col. address delay | tCDL(rriin) | 1 | CLK | 2 |
| Last data in to burst stop | tBDL(rTiin) | 1 | CLK | 2 |
| Col. address to col. address delay | tCCD(rTiin) | 1 | CLK | 4 |
| Number of valid output data | CAS latency=3 | 2 | | |
| Number of valid output data | CAS latency=2 | 1 | ea | 5 |
| Number of valid output data | CAS latency=l | 0 |
| | | | | | | |
