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NOTES 'Sample tested at 250C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% t0 90% of VDD) and timed from a voltage level of l.6 V. 2The SCLK maximum frequency is 15 MHz for Mode o operation for 220 kSPS throughput with VDRIVE = 5 V + 5%, SCLK = 13 MHz with VDRIVE = 2.7 V t0 3.6 V. The mark/space ratio for SCLK is specified for at least 40% high time (with corresponding 60% low time) or 40% low time (with corresponding 60% high time). As the SCLK frequency is reduced, the marldspace ratio may vary, provided limits are not exceeded. Care must be taken when interfacing to account for the data access time, t4, and the set-up time required for the users processor. These two times will determine the maximum SCLK frequency that the user's system can operate with. See Serial Interface section. 3Measured with the load circuit of Figure l and defined as the time required for the output to cross 0.8 V or 2.0 V. 4t6 and t8 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure l. The measured number is then extrapo- lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 6 and t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 5MarldSpace ratio for the SCLK input is 40/60 t0 60/40. Specifications subject to change without notice.