| VCC | Operating Supply Voltage Range | | | 3.1 5.5 | V |
| VVIDfT1 | VIDO-VID4 Logic Threshold Voltage | vCC= 3.3V | | 0.4 1.2 2 | V |
| VVID(LEAK) | VIDO-VID4 Leakage Current | VVIDO-VVID4 = VCC | | 0.01 ±1 | |
| O\/OSENSE | DAC Output Accuracy | VOSENSE Programmed from 1.05V t0 1.825V (Note 5), Vcc = 5V | | - 0.25 0 0.25 | |
| RPULLUP | Pull-Up Resistance on VID | VDIODE = 0.6V (Note 6) | | 28 40 56 | kI |
| RVID | Resistance from VOSENSE to VFB | | | 6 10 14 | k |
| lvCC | Supply Current | (Note 7) | | 1 10 | |
| | | | | |
No Wrtie-Interrupted by Read Function 4 DQS's ( 1DQS / Byte ) Data l/0 transactions on both edges of Data strobe DLL aligns DQ and DQS transitions with Clock transition Edge aligned data & data strobe output Center aligned data & data strobe input DM for write masking only Auto & Self refresh 32ms refresh period (4K cycle) 144-Ball FBGA Maximum clock frequency up t0 450MHz Maximum data rate up t0 900Mbps/pin