| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| NACK100M50V5X6.1TR13F | NIC | 07+ | 36000 |
|
NACK100M50V5X6.1TR13F Datasheet
NACK100M50V5X6.1TR13F Price 1 10 years mmimum data retention in the absence of external power ' Data is automatically protected during power loss ' Directly replaces 2k x 8 volatile static RAM or EEPROM ' Unlimited write cycles ' Low-powerCMOS I JEDEC standard 24-pin DIP package I Read and write access times as fast as 100 ns ' Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ' Full+10% Vcc operating range (DS1220AD) ' Optional+5% Vcc operating range (DS1220AB) ' Optionalindustrialtemperature range of -400C to +850C, designated IND NACK100M50V5X6.1TR13F on stock SIGNAL DESCRIPTIONS See Figure l and Table l. Addresslnputs (AO-A17). The address signal A17 is the MSB and AO the LSB. In the Asynchronous mode the addresses must be stable before Chip Enable E and Write Enable W go to VIL. They must remain stable during the read or write cycle. In the Synchronous modes, the addresses are latched by the rising edge of the System Clock CLK when both Latch Burst Address LBA and Chip Enable E are at VIL. The addresses are latched for a read operation if Write/Read WR is at VIH or for a write operation when it is at VIL. Data Input/Output (DQO-DQ31). The data signal DQ31 is the MSB and DQO the LSB. Commands are input on DQO-DQ7. Data input is a Double-Word to be programmed in the memory or an Instruction command to the Command Interface. Data is read from the Main or Overlay memory blocks, the Status Register or the Electronic Signature. In the Asynchronous mode data is read when the addresses are stable and Chip Enable E and Out- put Enable G are at VIL. Commands or address/ data are written when Chip Enable E and Write W are at VIL. In the Synchronous mode, after addresses are latched, data is read on a rising edge of the Sys- tem Clock CLK when Chip Enable E is at VIL and if Output Enable was at VIL on the previous rising clock edge. Data is written on a rising edge of the SystemClock CLK when Chip Enable E and Write Enable W are at VIL. The outputs are high imledance when Chip En- able E or Output Enable G are at VIH, orwhen Out- put Disable ~D is at VIL. Outputs are also high impedance when System Reset RP is at VIL.
|
