| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| NACK331M25V8X10.5TR13F | NIC | 07+ | 36000 |
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NACK331M25V8X10.5TR13F Datasheet
NACK331M25V8X10.5TR13F Price
NACK331M25V8X10.5TR13F on stock For processing the eight interrupt levels, the MARC4 includes an interrupt controller with tw0 8-bit wide interrupt pending and interrupt active registers. The interrupt controller samples all interrupt requests during every non-l/0 instruction cycle and latches these in the interrupt pending register. If no higher priority interrupt is present in the interrupt active register, it signals the CPU to interrupt the current program execution. If the inter- rupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the service routine is executed and the current PC is saved on the return stack. Following the CIC5 are two sets of fdters. Each set has a non- decimating FIR filter and a decimate-by-2 half-band filter. The FIRl filter provides about 30 dB of rejection, while the HB1 filter provides about 77 dB of rejection. They can be used together to achieve a 107 dB stopband alias rejection, or they can be individually bypassed to save power. The FIR2 filter provides about 30 dB of rejection,while the HB2 filter provides about 65 dB of rejection. The filters can be used either together |
