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PC2650 Datasheet

lRank N M L K
lRange 30 t0 60 40tD 80 60 t0 120 100 t0 200


PC2650 Price
These devices feature the ability to clamp dangerous high voltage short term transients such as produced by directed or radiated electro-static-discharge phenomena before entering sensitive component regions of a circuit desig n. They are small economicaltransient voltage suppressors targeted primarily for short term transients below a few microseconds while still achieving significant peak-pulse-power capability as seen in Figure #1.
PC2650 on stock

Collector-Emitter Breakdown Voltage(l) (IC = 1.0 mAdc, lB = 0) V(BR)CEO 40 Vdc
Collector-Base Breakdown Voltage (IC = 0.1 mAdc, IE = 0) \/(BR)CBO 60 Vdc
Emitter-Base Breakdown Voltage (IE = 0.1 mAdc, lC = 0) V(BR)EBO 6.0 Vdc
Base Cutoff Current (VCE = 35 Vdc, VEB = 0.4 Vdc) IBEV 0.1 D:Adc
Collector Cutoff Current (VCE = 35 Vdc, VEB = 0.4 Vdc) ICEX O1 D:Adc


OPERATION - READ CYCLE The DS1384 executes a read cycle whenever WE iS inactive (high) and CE and OE are active (low). The unique address specified by the address inputs (AO-A16) defines which of the on-chip 64 RTC/RAM or external SRAM locations is to be accessed. When the address value presented to the DS1384 is in the range of OOOOOH through 0003FH, one of the 64 0n-chip registers will be selected and valid data will be available to the eight data output drivers within tACC (access time) after the address input signal is stable, providing that the CE and OE access times are also satisfied. If they are not, then data access must be measured from the latter occurring signal (CE or OE) and the limiting parameter is either tco for CE or tOE for OE rather than the address access time. When one of the on-chip registers is selected for read, the OER signal will remain inactive throughout the read cycle.