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PC28F320J3D75SB48 Datasheet
I Description The LH5821/LH5822/LH5823 are CMOS drirr- er LSIs for LCD dot matrix display. Any one of display duty ratio, 1/7 1/20 can be selected by programming. Write and read to/from the built-in RAM of dis- play data can be made only by 3 signals, serial data, synchronous signal, and transfer clock. The LH5826 is available for segment output ex- pansiom
PC28F320J3D75SB48 Price

Parameter Symbol Min Typ Max Unit
Single Speed Mode (2 t0 50 kHz sample rates)
Passband (-0.1 dB) (Note 5) 0 .0.47 Fs
Passband Ripple ±0.035 dB
Stopband (Note 5) 0.58 Fs
Stopband Attenuation -95 dB
Total Group Delay (Fs = Output Sample Rate) tgd 1 2/Fs S
Group Delay Variation vs. Frequency Atgd 0.0 Lis
Double Speed Mode (50 t0 100 kHz sample rates)
Passband (-0.1 dB) (Note 5) 0 .0.45 Fs
Passband Ripple ±0.035 dB
Stopband (Note 5) 0.68 Fs
Stopband Attenuation -92 dB
Total Group Delay (Fs = Output Sample Rate) tgd 9/Fs S
Group Delay Variation vs. Frequency Atgd 0.0 LLS
Quad Speed Mode (100 t0 192 kHz sample rates)
Passband (-0.1 dB) (Note 5) 0 .0.24 Fs
Passband Ripple ±0.035 dB
Stopband (Note 5) 0.78 Fs
Stopband Attenuation -97 dB
Total Group Delay (Fs = Output Sample Rate) tgd · 5/Fs S
Group Delay Variation vs. Frequency Atgd 0.0 Lis
High Pass Filter Characteristics
Frequency Response -3.0 dB -0.13 dB (Note 6) 1 20 Hz Hz
Phase Deviation @ 20 Hz (Note 6) 1 0 Deg
Passband Ripple 0 dB
Filter Setting Time 1 0i/Fs S


PC28F320J3D75SB48 on stock

Ordering Code Package Type Operating Range
CY2304NZZC-1 8-pin TSSOP Commercial, OoC t0 700C
CY2304NZZC-1T 8-pin TSSOP - Tape and Reel Commercial, OoC t0 700C
CY2304NZZI-1 8-pin TSSOP Industrial, -400C t0 85aC
CY2304NZZI-1T 8-pin TSSOP - Tape and Reel Industrial, -400C t0 85aC


The LH28F004SU-Z1 provides user-selectable block locking to protect code or data such as Device Drivers, PCMCIA card information, ROM-Executable OS or Application Code. Each block has an associated non- volatile lock-bit which determines the lock status of the block. In addition, the LH28F004SU-Z1 has a software controlled master Write Protect circuit which prevents any modifications to memory blocks whose lock-bits are set.