MOTMap-19  > PC3410

suppliers of PC3410 and PDF data of PC3410

Part Numbert Mfg Packt D/C Descriptiont Qty Company/Contact  

PC3410 Datasheet
The 24LC024/24LC025 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previ- ous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the 24LC024/24LC025 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC024/24LC025 discontinues transmission (Figure 8-1).
PC3410 Price
O TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBAproducts, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. ! The products described in this document are subject to foreign exchange and foreign trade laws. O The Tnformation contained herein is presented only as a guide _for the appljcations of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights oTthe third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. O T~e irTformation contained herein is subject to change without notice.
PC3410 on stock

Limits
Symbol Parameter Condition Min Max Unit
VDD Power Supply Voltage 3.135 3.465 v
VDDO= 3.3V 3.135 3.465 V
VDDQ I/O Buffer Power Supply Voltage VDDC!= 2.5V 2.375 2.625
VDDO = 3.135~3.465V V
VIH High-Ievel Input Voltage VDDO = 2.375~2.625V 0.65'VDDQ VDDo+0.3*
VDDO = 3.135~3.465V V
VIL Low-Ievel Input Voltage VDDC! = 2.375~2.625V -0.3* 0.35VDDQ
VOH High-Ievel Output Voltage IOH= -2.OmA vDDo-0.4 v
VOL Low-Ievel Output Voltage IOL= 2.OmA 0.4 v
|Ll Input Current except ZZ and LBO# Vi= OVVDDC! 10
Input Current of LBO# Vi= OVVDDC! 10 pA
Input Current of ZZ Vi= OVVDDC! 10
ILO Off-state Output Current Vi (G# VIH, Vo = OV ~ VDDC! 10 pA
lcci Power Supply Current : Operating Device selected; Output Open VI<VIL or VI>VIH ZZ<VIL 6.Ons cycle(167MHz) 340 mA
lcc2 Power Supply Current : Deselected Device deselected VI<VIL or VI>VIH ZZ<VIL 6.Ons cycle(167MHz) 90 mA
ICC3 CMOS Standby Current (CLK stopped standby mode) Device deselected; Output Open Vi<Vss+0.2V or VI>VDDo-0.2V CLK frequency=OHz, All inputs static 20 mA
ICC4 Snooze Mode Standby Current Snooze mode ZZ>VDDcl-0.2V, LBO#>VDD-0.2V 20 mA
lccs Stall Current Device selected; Output Open CKE#>VIH Vi<Vss+0.2V or Vi>VDDcl-0.2V 6.Ons cycle(167MHz) 45 mA


PARAMETER bUBGROUPS bYMBOL MIN MAX UNITS
Address Access Time CE = OE = VIL, WE = VIH -120 -150 9. 10, 11 tACC 120 150 ns
CE to Output Delay OE = VIL, WE = VIH -120 -150 9. 10, 11 tCE 120 150 ns
OE to Output Delay CE = VIL, WE = VIH -120 -150 9. 10, 11 tOE 0 0 75 75 ns
Output Hold from Address CE = OE = VIL, WE = VIH -120 -150 9. 10, 11 tOH 0 0 ns
OE (CE) High to Output Float CE = VIL, WE = VIH 2 -120 -150 9. 10, 11 lDF 0 0 50 50 ns