| SYMBOL | PARAMETER | MIN | Typ | MAX | UNIT | CONDITION |
| THrisc. THfal, | Host clock Rise and Fall Time | 0.4 | | 1.6 | ns | 20pfload/CPU and PCI outputs |
| THCP | Host Clock Period | 15/16.7 | | | ns | Measured at l.25V, 66/60MHz |
| THCH | Host Clock High Time | 5.2/6.0 | | | ns | Measured at 2.OV, 66/60MHz |
| THCL | Host Clock Low Time | 5.0/5.8 | | | ns | Measured at 0.4V, 66/60MHz |
| Duty Cycle | Duty cycle | 45 | 50 | 55 | % | Refer to Notes below |
| THSKW | Buffer out Skew All Host CLK | | | 250 | ps | Refer to Notes below |
| TJAB | Jitter absolute, Host clock | | | 250 | ps | Refer to Notes below |
| TSTB | Host/PCI clock stabilization from power-up | | | 3 | ms | Refer to Notes below, VDDL=3.3V |
| Toff | Host to PIC Offset | 1.0 | | 4.0 | ns | Refer to Notes below |
| THSSKW | Host to SDRAM skew | | | 250 | ps | Refer to Notes below |
| TPCP | PCI clock period | 30/33.3 | | | ns | Measured at l.5V, 66/60MHz |
| TPCH | PCI clock High Time | 12/13.3 | | | ns | Measured at 2.4, 66/60MHz |
| TPCL | PCI clock Low Time | 12/13.3 | | | ns | Measured at 0.4, 66/60MHz |
| TPSKW | Buffer out skew all PCICLK | | | 500 | ps | Refer to Notes below |
| Iol | Switching Current Low | TBD | 60 | TBD | mA | V01=1.5V |
| Ioh | Switching Current High | TBD | 60 | TBD | mA | Voh=1.5V |
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