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VDD = +2.5V+0.2V VDDQ = +2.5V+0.2V Bidirection al data strob e (DQ S) tran smitted/ received with data, i.e., source-syn chronou s data capture (x16 has two - one per byte) In tern al, pip elin ed double -data-rate (DD R) architecture ; two data accesses p er clock cycle Differential clo ck in p uts (CK an d CK#) Comm ands entered on each p o sitive CK edge DQS edge-aligned with data for READs; center- aligned with data for WRITEs DLL to align DQ and DQS tran sition s with CK Four in tern al b an ks for concurrent operation Data mask (D M) for m askin g write data (x16 has two -one per byte) Pro gram m able burst len gths: 2, 4, or 8 Auto Refresh and SelfRefresh Modes Lon ger lead TSOP for imp roved reliability (OCPL) 2.5VI/O (SSTL_2 compatible) Concurrent auto precharge option is supported tRAS lo cko u t supp orted (tRAP = tRCD)
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