| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| PC50 | VISHAY | TO-247 | 08+ | 4000 |
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| PC50 | VISHAY | TO-247 | 08+ | 4000 |
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| PC50 | VISHAY | TO-247 | 08+ | 2000 |
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| PC50 | VISHAY | TO-247 | 08+ | 2000 |
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| PC50 | . | SOP8 | 09+ | 优势库存，欢迎来电！ | 4921 |
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| PC50 | . | SOP8 | 09+ | 752 |
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| PC50 | PHILIPS | OO | 1 |
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| PC50 | SOP- 8 | 04+ | 7 |
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| PC50 | Skype:gtuitgah@163.com | 1-2days | 500 |
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| PC50 | 18 |
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| PC50 | . | 2004+ | 1250 |
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| PC50 | SMD | 06+ | 500 |
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| PC50 | SMD | 07+ |
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| PC50 | 798 | SMD |
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| PC50 | SOP- 8 |
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PC50 Datasheet After the luma prefilter, the bandlimited luma signal is sampled onto a set ofcapacitors at twice the master reference clock rate. After an appropriate delay, the data is read offthe delay line, reconstructing the luma signal. T he 8F SC oversampling of this delay line limits the amount ofjitter in the reconstructed sync output. The clocks driving the delay line are reset once per video line during the burst flag. T he output ofthe luma path will remain unchanged during this period and will not respond to changing RGB inputs. PC50 Price Notes: 1) All typical values are at 5.0 V and 250C unless otherwise noted. 2) VO H and VO L can be set by the extemal resistor values on the PECL outputs. 3) IDD includes the current through the external resistors, which can be modified. 4) The phase relationship between input and output can change at power up. For a fixed phase relationship, see one ofthe ICS zero delay buffers. PC50 on stock TJ, JUNCTION TEMPERATURE Figure 15. Typical switching energy losses as a function ofjunction temperature (inductive load, VCE=400V, VGE = 0/15V, /C = 6A, RG = 2301, Dynamic test circuit in Figure E)
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