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PC5051M Datasheet

l PP7	PP6	PP5	PP4	PP3	PP2	PP1	PPO
l O	0	1	0	1	0	0	0

PC5051M Price

SYMBOL	PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
IGT IL IH VT VGT ID, IR	Gate trigger current Latching current Holding current On-state voltage Gate trigger voltage Off-state leakage current	VD = 12 V; IT = 0.1 A VD = 12 V; IGT = 0.1 A VD = 12 V; IGT = 0.1 A IT = 40 A VD = 12 V; IT = 0.1 A YD - vDRM(max)j h =_O\1_A, T: ;j251ag5 0C VD = VDRM(max); VR = VRRM(max	0.25	3 25 15 1.4 0.6 0.4 0.2	32 80 60 1.75 1.5 1.0	mA mA mA V V V mA

PC5051M on stock

5632 bl 07 3 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or l/0 pin cannot exceed VDDO during power supply ramp up. 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

The Tl Divider uses the 12.352MHz signal to generate two As its master clock, the PT7A4401C uses either an external clock signals, C1.5 and C3. They have a nominal 50% duty clock source or an external crystal and a few discrete compo- cycle. nents with its internal oscillator.

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