PC703V3 Datasheet| | | j | | | N VJIN | | | | | | | | R | | | | | Tc= ,Sir | 250( iale | | | | | | L | | | nonrepeiiiivel pulse | | | | | | | | | | | | | | |
PC703V3 Price Input to both the cycle-by-cycle and overcurrent fault current sense comparators. The cycle-by-cycle current limit comparator is the mechanism by which the VEA's output voltage commands the level ofinductor or transformer current during a given "on" interval, thereby regulating the overall circuit's output. This comparatorforms theinnerloop of the two loops used in current-mode regulation. PC703V3 on stock| | | | | | | | | | | | | | | 10V\ | | | | | | 15V\ 20 V \ | § | | | | | | ' | t{ | | | | | j | j|Jj | | Jj | | __ | | | | | | | |
| | | | Ta= 250C | Ta = - 40~850C | | | PARAMETER | SYMBOL | I n) i lui\iui i IUI-J | Vcc (V) | MIN. | TYP. | MAX. | MIN. | MA× | UNIT | | Output Transition Time | tTLH tTHL | | 2.0 4.5 6.0 | | 30 8 7 | 75 1 5 13 | | 95 19 16 | | | Propagation Delay Time (IN-AO, Al, A2) | tpLH tpHL | | 2.0 4.5 6.0 | | 52 19 1 5 | 1 50 30 26 | | 190 38 33 | | Propagation Delay Time (IN- EO, GS) | tpLH tpHL | | 2.0 4.5 6.0 | | 52 19 1 5 | 1 50 30 26 | | 190 38 33 | ns | | Propagation Delay Time ( El- EO) | tpLH tpHL | | 2.0 4.5 6.0 | | 40 14 1 1 | 1 1 5 23 20 | | 145 29 25 | | Propagation Delay Time ( El- GS) | tpLH tpHL | | 2.0 4.5 6.0 | | 40 14 12 | 1 1 5 23 20 | | 145 29 25 | | Propagation Delay Time ( El- AO, Al, A2) | tpLH tpHL | | 2.0 4.5 6.0 | | 40 14 12 | 1 1 5 23 20 | | 145 29 25 | | Input Capacitance | CIN | | | 5 | 10 | | 10 | | | Power Dissipation Capacitance | CPD (1) | | | 55 | | | | pF | | | | | | | | | | |
|
