PC74F0 PC74F0 PC74F0 Datasheet| Pin | Name | Type | Description | | 1. 15 | GND | Gro und | Ground (OV) | | 2, 3, 19, 21, 22, 24, 25 | NU | I | Not Used (should be connected to ground) | | 4 | REF | I | Reference Input (TTL compatible): Input reference signals | | 5. 18 | V | Power | Power Supply (+5V) | | 6 | OSCo | 0 | Oscillator Master Clock Output (CMOS): Output of 20MHz master clock | | 7 | OSCi | I | Oscillator Master Clock Input (CMOS): Input of 20MHz master clock (can be connected directly to a clock source) | | 8 | F16 | 0 | Frame Pulse Output (CMOS Compatible): 8kHz framing output pulse that indicates the start of the ST-BUS frame. The pulse width is based upon the period of the 16.384MHz synchronization clock. | | 9 | | 0 | Frame Pulse Output (CMOS Compatible): 8kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 4.096MHz synchronization clock. | | 10 | F8 | 0 | Frame Pulse Output (CMOS Compatible): 8kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 8.192MHz synchronization clock. | | 11 | C1.5 | 0 | 1.544MHz Clock (CMOS Compatible) | | 12 | C3 | 0 | 3.088MHz Clock (CMOS Compatible) | | 13 | C2 | 0 | 2.048MHz Clock (CMOS Compatible) | | 14 | C4 | 0 | 4.096MHz Clock (CMOS Compatible) | | 16 | C8 | 0 | 8.192MHz Clock (CMOS Compatible) | | 17 | C16 | 0 | 16.384MHz Clock (CMOS Compatible) | | 20 | NC | 0 | Not Connected: Make no connection to this pin. | | 23 | MS | I | Mode Select (TTL Compatible): This input selects the operation mode of the device, i.e., Normal or Freerun. Refer to Table 4. | | 26 | FS2 | I | Frequency Select 2 (TTL Compatible): This input, together with FSl, selects the frequency of the input reference signal, either 8kHz, 1.544MHz or 2.048MHz. Refer to Table 3. | | 27 | FS1 | I | Frequency Select l (TTL Compatible): Refer to the pin description of FS2. | | 28 | RST | I | Reset (CMOS Input Schmitt Trigger): Reset the device when at low level. The reset is needed when power-up or when frequency select input change to ensure proper operation. The time constant for a power-up reset circuit must be a min. of five times the rise time of the power supply. In normal _operation, the RST pin must be held low for a min. of300 ns to reset the device. When RST at low level, all outputs are fixed at HIGH. | | | | |
PC74F0 PC74F0 PC74F0 Price Sequential Row Read is available only on K9F2808UOC_Y,P or K9F2808UOC_V,F : After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10Us again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Readl operation and spare sixteen bytes of each page may be sequentially read. The Sequential Read l and 2 0peration is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row read operation. PC74F0 PC74F0 PC74F0 on stock| k | VG | S= 10,9,8 | 7.6V | | | | | | | | | lj | | | | 5V | | | | | | | | l | | | | 4V | | j | | | | 3V | | | | | |
| Parameter | Y Versionsl | Units | Conditions/Comments | | STATIC PERFORMANCE No Missing Codes Output Noise Integral Nonlinearity Unipolar Offset Error Unipolar Offset Drift3 Bipolar Zero Error Bipolar Zero Drift3 Positive Full-Scale Error4 Full-Scale Drift3' 5 Gain Error6 Gain Drift3' 7 Bipolar Negative Full-Scale Error2 Bipolar Negative Full-Scale Drift3 | 24 18 15 12 See Tables I to IV +0.001 See Note 2 0.4 O.l See Note 2 0.4 O.l See Note 2 0.4 O.l See Note 2 0.2 +0.0015 +0.003 1 0.6 | Bits min Bits min Bits min Bits min Bits min % of FSR max ccV/lC typ ccV/YC typ ccV/YC typ ccV/YC typ ccV/YC typ ocV/YC typ ppm of FSRJ YC typ % of FSR max % of FSR max ccV/lC typ ocV/YC typ | Guaranteed by Design. For Filter Notches " 60 Hz For Filter Notch = 100 Hz For Filter Notch = 250 Hz For Filter Notch = 500 Hz For Filter Notch = 1 kHz Depends on Filter Cutoffs and Selected Gain Filter Notches " 60 Hz. For Gains of l, 2, 4 For Gains of 8, 16, 32, 64, 128 For Gains of l, 2, 4 For Gains of 8, 16, 32, 64, 128 For Gains of l, 2, 4 For Gains of 8, 16, 32, 64, 128 AVDD = 5 V. Typically +0.0004% AVDD = 3 V. Typically +0.0004% For Gains of l t0 4 For Gains of 8 t0 128 | | ANALOG INPUTS/REFERENCE INPUTS Input Common-Mode Rejection (CMR)8 Normal-Mode 50 Hz Rejection8 Normal-Mode 60 Hz Rejection8 Common-Mode 50 Hz Rejection8 Common-Mode 60 Hz Rejection8 Absolute/Common-Mode REF IN Voltages Absolute/Common-Mode AIN Voltages' 9 Absolute/Common-Mode AIN Voltages' 9 AIN DC Input Current8 AIN Sampling Capacitance8 AIN Differential Voltage Rangelo AIN Input Sampling Rate, fs Reference Input Range REF IN(+) - REF IN(-) Voltage REF IN(+) - REF IN(-) Voltage REF IN Input Sampling Rate, fs | 90 100 100 150 150 AGND to AVDD AGND - 30 mV AVDD + 30 mV AGND + 50 mV AVDD - 1.5 V 1 O to +VREF/GAIN'1 +VREF/GAIN GAIN x fCLK m/64 fCLK IN/8 1/1.7 5 1/3 .5 fCLK IN/64 | dB min dB min dB min dB min dB min V min to V max V min V max V min V max nA max pF max nom nom V min/max V min/max | Specifications for AIN and REF IN Unless Noted At DC. Typically 102 dB. For Filter Notches of 10 Hz, 25 Hz, 50 Hz,+0.02 x fNOTCH For Filter Notches of 10 Hz, 30 Hz, 60 Hz,+0.02 x fNOTCH For Filter Notches of 10 Hz, 25 Hz, 50 Hz,+0.02 x fNOTCH For Filter Notches of 10 Hz, 30 Hz, 60 Hz, +0.02 x fNOTCH BUF Bit of Setup Register = O BUF Bit of Setup Register = 1 Unipolar Input Range (B/U Bit of Filter High Register = 1) Bipolar Input Range (B/U Bit of Filter High Register = O) For Gains of l t0 4 For Gains of 8 t0 128 AVDD = 2.7 V t0 3.3 V. VREF = 1.25 +1% for Specified Performance AVDD = 4.75 V t0 5.25 V. VREF = 2.5 +1% for Specified Performance | | LOGIC INPUTS Input Current AllInputs Except MCLK IN VIND Input Low Voltage VINH, Input High Voltage SCLK & DIN Only (Schmitt Triggered Input) VT+ VT- VT+ - VT- SCLK & DIN Only (Schmitt Triggered Input) VT+ VT- VT+ - VT- MCLK In Only VIND Input Low Voltage VINH, Input High Voltage MCLK In Only VIND Input Low Voltage VINH, Input High Voltage | +10 0.8 0.4 2.4 1.4/3 0.8/1.4 0.4/0.8 1/2.5 0.4/1.1 0.375/0.8 0.8 3.5 0.4 2.5 | oGA max V max V max V min V min V minN max V minN max V minN max V minN max V minN max V minN max V max V min V max V min | DVDD = 5 V DVDD = 3 V DVDD = 5 V DVDD = 3 V DVDD = 5 V NOMINAL DVDD = 3 V NOMINAL DVDD = 5 V NOMINAL DVDD = 3 V NOMINAL | | LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage VOD Output Low Voltage VOH, Output High Voltage | O4 0.4 4 | V max V max V min | ISINK = 800 ccA with DVDD = 5 V. Except for MCLK OUT12 ISINK = 100 0A with DVDD = 3 V. Except for MCLK OUT12 ISOURCE = 200.A with DVDD = 5 V. Except for MCLK OUTI2 | | | | |
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