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PC74F245DWR Datasheet

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PC74F245DWR Price

Reverse Voltage VR 1 0 V
Forward Current IF 2 mA
Optical power into the optical port Pport 1.5 mW


PC74F245DWR on stock

Gate threshold voltage VGE = VCE,/C = 4 mA E(th) 4.5 5.5 6.5 V
Collector-emitter saturation voltage VGE = 15 V, /C = 100 A, Tj = 25 aC VGE = 15 V, /C = 100 A, Tj = 125 0C VCE(sat) 2.5 3.1 3 3.7
Zero gate voltage collector current VCE = 1200 V, VGE = 0 V, Tj = 25 aC VCE = 1200 V, VGE = 0 V, Tj = 125 aC /CES 1.5 6 2 mA
Gate-emitter leakage current VGE = 20 V, VCE = OV /GES 400 nA


Set VREF t0 0 volts. With the load connected and the PWM current control operating in slow decay mode, use an oscilloscope to measure the time the output is low (sink ON) for the output that is chopping. This is the typical minimum on time (tON(min)typ) for the device. The CT then should be increased until the measured value of tON(min) iS equal to tON(min)max as specified in the electrical characteristics table. When the new value of CT has been set, the value of RT should be decreased so the value for tOFF = RTCT (with the artificially increased value of CT) is equal to the nominal design value. The worst-case load- current regulation then can be measured in the system under operating conditions.