| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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PC74F373DT PC74F373DT PC74F373DT Datasheet The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into four 128Mbit separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining the conventional 512 byte structure. The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document. PC74F373DT PC74F373DT PC74F373DT Price Notes 1. X means "Don't Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. PC74F373DT PC74F373DT PC74F373DT on stock Compliance Testing Inductance due to long leads on type approval equipment can cause ringing and overshoot that leads to testing problems. Small amounts of capacitance and damping resistors can be included in the application without com- promising the normal electrical performance of the LTC4557 0r smart card system. Generally a ioo I resistor and a 20pF capacitor will accomplish this as shown in Figure 2. Digitalto Analog Converter The built-in digital to analog converter allows the adjustment of the output voltage from l.30V t0 2.05V with 50mV binary steps and from 2.10V t0 3.50V with 100mV binary steps as shown in the previous table l. The internal reference is trimmed to ensure the precision of l%. |
