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V2) This variable represents the programmed width of the PSEN pulse as determined by the CRl and CRO bits or the CRAl, CRAO, and ALEW bits in the BTRL register. - For a bus cycle with no ALE, V2 = 1 if CRl/0 = 00, 2 if CRl/0 = 01, 3 if CRl/0 = 10, and 4 if CRl/0 = 11. Note that during burst mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of determining peripheral timing requirements. - For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRAl/0 = 00, 3 if CRAl/0 = 01, 4 if CRAl/0 = 10, and 5 if CRAl/0 = 11) minus the number of clocks used by ALE (V1 + 0.5). Example: If CRAl/0 = 10 and ALEW = 1, the V2 = 4 - (1.5 + 0.5) = 2. V3) This variable represents the programmed length of an entire code read cycle with ALE. This time is determined by the CRAl and CRAO bits in the BTRL register. V3 = the total bus cycle duration (2 if CRAl/0 = 00, 3 if CRAl/0 = 01, 4 if CRAl/0 = 10, and 5 if CRAl/0 = 11). V4) This variable represents the programmed length of an entire code read cycle with no ALE. This time is determined by the CRl and CRO bits in the BTRL register. V4 = 1 if CRl/0 = 00, 2 if CRl/0 = 01, 3 if CRl/0 = 10, and 4 if CRl/0 = 11. V5) This variable represents the programmed length of an entire data read cycle with no ALE. this time is determined by the DRl and DRO bits in the BTRH register. V5 = 1 if DRl/0 = 00, 2 if DRl/0 = 01, 3 if DRl/0 = 10, and 4 if DRl/0 = 11. V6) This variable represents the programmed length of an entire data read cycle with ALE. The time is determined by the DRAl and DRAO bits in the BTRH register. V6 = the total bus cycle duration (2 if DRAl/0 = 00, 3 if DRAl/0 = 01, 4 if DRAl/0 = 10, and 5 if DRAl/0 = 11). V7) This variable represents the programmed width of the RD pulse as determined by the DRl and DRO bits or the DRAl, DRAO in the BTRH register, and the ALEW bit in the BTRL register. Note that during a 16-bit operation on an 8-bit external bus, RD remains low and does not exhibit a transition between the first and second byte bus cycles. V7 still applies for the purpose of determining peripheral timing requirements. The timing for the first byte is for a bus cycle with ALE, the timing for the second byte is for a bus cycle with no ALE. - For a bus cycle with no ALE, V7 = 1 if DRl/0 = 00, 2 if DRl/0 = 01, 3 if DRl/0 = 10, and 4 if DRl/0 = 11. - For a bus cycle with an ALE, V7 = the total bus cycle duration (2 if DRAl/0 = 00, 3 if DRAl/0 = 01, 4 if DRAl/0 = 10, and 5 if DRAl/0 = 11) minus the number of clocks used by ALE (V1 + 0.5). Example: If DRAl/0 = 00 and ALEW = 0, then V7 = 2 - (0.5 + 0.5) = 1. V8) This variable represents the programmed width of the WRL and/or WRH pulse as determined by the WMl bit in the BTRL register. V8 1 if WMl = 0, and 2 if WMl = 1. V9) This variable represents the programmed address setup time for a write as determined by the data write cycle duration (defined by DWl and DWO or the DWAl and DWAO bits in the BTRH register), the WMO bit in the BTRL register, and the value of V8. - For a bus cycle with an ALE, V9 = the total bus write cycle duration (2 if DWAl/0 = 00, 3 if DWAl/0 = 01, 4 if DWAl/0 = 10, and 5 if DWAl/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WMO = 0 and l if WMO = 1). Example: If DWAl/0 = 10, WMO = 1, and WMl = 1, then V9 = 4-1 -2 = 1. - For a bus cycle with no ALE, V9 = the total bus cycle duration (2 if DWl/0 = 00, 3 if DWl/0 = 01, 4 if DWl/0 = 10, and 5 if DWl/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WMO = 0 and l if WMO = 1). Example: If DWl/0 = 11, WMO = 1, and WMl = 0, then V9 = 5-1 -1 = 3. V10) This variable represents the length of a bus strobe for calculation of WAIT setup and hold times. The strobe may be RD (for data read cycles), WRL and/or WRH (for data write cycles), or PSEN (for code read cycles), depending on the type of bus cycle being widened by WAIT. V10 = V2 for WAIT associated with a code read cycle using PSEN. V10 = V8 for a data write cycle using WRL and/or WRH. V10 = V7-1 for a data read cycle using RD. This means that a single clock data read cycle cannot be stretched using WAIT. If WAIT is used to vary the duration of data read cycles, the RD strobe width must be set to be at least two clocks in duration. Also see Note 4. V11) This variable represents the programmed write hold time as determined by the WMO bit in the BTRL register. V11 = 0 if the WMO bit = 0, and l if the WMO bit = 1. V12) This variable represents the programmed period between the end of the ALE pulse and the beginning of the WRL and/or WRH pulse as determined by the data write cycle duration (defined by the DWAl and DWAO bits in the BTRH register), the WMO bit in the BTRL register, and the values of Vl and V8. V12 = the total bus cycle duration (2 if DWAl/0 = 00, 3 if DWAl/0 = 01, 4 if DWAl/0 = 10, and 5 if DWAl/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WMO = 0 and l if WMO = 1), minus the width of the ALE pulse (V1). Example: If DWAl/0 = 11, WMO = 1, WMl = 0, and ALEW = 1, then V12 = 5-1 -1 - 1.5 = 1.5. V13) This variable represents the programmed data setup time for a write as determined by the data write cycle duration (defined by DW1 and DWO or the DWAl and DWAO bits in the BTRH register), the WMO bit in the BTRL register, and the values of Vl and V8. - For a bus cycle with an ALE, V13 = the total bus cycle duration (2 if DWAl/0 = 00, 3 if DWAl/0 = 01, 4 if DWAl/0 = 10, and 5 if DWAl/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WMO = 0 and l if WMO = 1), minus the number of clocks used by ALE (V1 + 0.5). Example: If DWAl/0 = 11, WMO = 1, WMl = 1, and ALEW = O, then V13 = 5 -1 -2 -1 = 1. - For a bus cycle with no ALE, V13 = the total bus cycle duration (2 if DWl/0 = 00, 3 if DWl/0 = 01, 4 if DWl/0 = 10, and 5 if DWl/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WMO = 0 and l if WMO = 1). Example: If DWl/0 = 01, WMO = 1, and WMl = 0, then V13 = 3- 1 -1 = 1. 3. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA User Guide section on the External Bus for details. 4. When code is being fetched for execution on the external bus, a burst mode fetch is used that does not have PSEN edges in every fetch cycle. Thus, if WAIT is used to delay code fetch cycles, a change in the low order address lines must be detected to locate the beginning of a cycle. This would be A3-AO for an 8-bit bus, and A3-A1 for a 16-bit bus. Also, a 16-bit data read operation conducted on a 8-bit wide bus similarly does not include two separate RD strobes. So, a rising edge on the low order address line (AO) must be used to trigger a WAIT in the second half of such a cycle.