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PC74F74D Datasheet

In addition to the four synchronous clocks, the Ultra37000 family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is available to all 16 macrocells. Each product term clock also supports user configurable polarity selection.
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Input pulse levels	VCC x 0.1 to VCc x 0.9
Input rise and fall times	10ns
Input and output timing levels	VCC x 0.5
Output load	Standard output load

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WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 713215 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 228, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 R FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikebur0 3-Chome, Toshima-Ku, Tokyo, Japan 171 Tel: ++ 81 3 3983 0641 IR SOUTHEAST ASIA: 315 0utram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: ++ 65 221 8371 http://www/irf.com/ Data and specifications subject to change without notice. 9/96

		Test Condition			Value
Symbol	Parameter				TA= 25C			-40 t0 850C		-55 t0 1250C		Unit
Symbol	Parameter	vcc (v)	CL (pF)		Min	Typ.	Max	Min	Max	Min	Max	Unit
tPLH	Propagation Delay	3.3(+)	15			5.1	7.5	1.0	8.5	1.0	9.05
tPHL	Time	3.3()	50			5.6	8.0	1.0	9.5	1.0	10.5
		5O(¨)	15			3.8	5.5	1.0	6.5	1.0	7.5	ns
		5O(¨)	50			4.3	6.5	1.0	7.5	1.0	8.5	ns
tPLZ	Output Disable	3.3(+)	15	RL =1 K l		5.4	8.0	1.0	9.0	1.0	10.0
tPHZ	Time	3.3()	50	RL =1 K l		7.9	11.5	1.0	12.5	1.0	13.5
		5O(¨)	15	RL =1 K l		3.6	5.0	1.0	6.0	1.0	7.0	ns
		5O(¨)	50	RL =1 K l		5.1	7.0	1.0	8.0	1.0	9.0	ns
		3.3(+)	15	RL =1 K l		5.4	7.6	1.0	9.5	1.0	10.5
tPZL	Output Enable	3.3()	50	RL =1 K l		5.9	8.5	1.0	10.0	1.0	11.0
tPZH	Time	5O(¨)	15	RL =1 K l		317	5.9	1.0	7.0	1.0	8.0	ns
tPZH	Time	5O(¨)	50	RL=1 Kl		4.1	6.5	1.0	7.5	1.0	8.5	ns

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