| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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PC74HC04PPHI PC74HC04PPHI PC74HC04PPHI Datasheet SYSTEM CONSIDERATIONS: During the switch between actiw and standby power condSons, Uansbnt current Waks are produced on the nsing and falling edges of chip enle. The magnitude of these Uansient current peaks is dependent on the output capacitance loading of the device. A O.lyF ceramic capacitor (high frvquenq low-int-emnt inductance) should be used on each device between Vcc and GND to minimize Uansient effects. In addidon, to overcome the voltage drop caused b)f the inductive effects of the printad circuit board traoas on EPROM arrays, a 4.7yF bulk eletrolytic capacitor should be used between Vcc and GND for ewry eight (8) davices. The location of ttw capacitor should be dose to where the ponr supphf is connectad to the array. PC74HC04PPHI PC74HC04PPHI PC74HC04PPHI Price
PC74HC04PPHI PC74HC04PPHI PC74HC04PPHI on stock 1) Regulation is measured at constant junction temperature, using pulse testing at a low duty cycle. Changes in output voltage due to heating effects are covered under thermal regulation specifications. Load regulation is measured at a point l/8" from the bottom of the package for the T0-3 and T0-66 packages, at the junction of the wide and narrow portion of the output lead for the SMD packages, and l/8" below the base of the package on the output pin of the T0-257 package.
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