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When a valid start bit is detected the receiver state machine allows the 1 6X divider circuit to continue counting o t0 1 5. Each time the receiver passes count 7 (the theoretical center of the bit time) another data bit is clocked into the receiver shift register until the proper number of bits have been received including the parity bit, if used, and l/2 stop bit. After the STOP BIT is detected the receiver state machine will wait until the next falling edge of the lX clock and then clock the assembled character and its status bits into the receiver FIFO on the next rising edge of the lX clock. The delay from the detection of the STOP BIT to the loading of the character to the RxFIFO will be from one half to one and one half Xl clock periods, or twice that if Xl/2 is used. Receiver Status Register bits for FIFO READY, FIFO FULL, parity error, framing error, break detect will also set at this time. The most significant bits for data characters less than eight bits will be set to zero.
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