When operating in the 16X mode and after the receiver has been enabled the receiver state machine will look for a high to low transition on the RxD input. The detection of this transition will cause the divider being driven by the 16X clock to be reset to zero and continue counting. When the counter reaches 7 the RxD input is sampled again and if still low a valid START BIT will be detected. If the RxD input is high at count 7 then an invalid start bit will have been sensed and the receiver will then look for another high to low transition and begin validating again.
| | | VDD>4.5V | VDD>4.OV | VDD>2.5V | |
| Symbol | ltem | MIN | MAX | MIN | MAX | MIN | MAX | Unit |
| tCES | CE set-up time | 175 | | 200 | | 400 | | ns |
| tCEH | CE hold time | 175 | | 200 | | 400 | | ns |
| tCR | CE inactive time | 350 | | 400 | | 800 | | ns |
| tSCK | SCLK clock cycle time | 350 | | 400 | | 800 | | ns |
| tCKH | SCLK high time | 175 | | 200 | | 400 | | ns |
| tCKL | SCLK low time | 175 | | 200 | | 400 | | ns |
| tCKS | SCLK to CE set-up time | 60 | | 80 | | 120 | | ns |
| tRE | Data output start time (from rising of SCLK) (from falling of SCLK) | | 120 | | 135 | | 300 | ns |
| tRR | Data output delay time (from rising of SCLK) (from falling of SCLK) | | 120 | | 135 | | 300 | ns |
| tRZ | Output floating time | | 120 | | 135 | | 300 | ns |
| tDS | Input data set-up time | 50 | | 60 | | 120 | | ns |
| tDH | Input data hold time | 50 | | 50 | | 80 | | ns |
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