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number of DWORD read transfers during either an Am5x86 CPU, PCI host bridge, or GP bus DMA read request that results in a hit to the read buer. A read buffer hit implies that at least one of the four bytes within a DWORD resulted in a read buffer hit. The performance monitor counts read buffer hits on the basis of an atomic read request during the same bus tenure, independent of burst length (i.e., complete cycle, regardless of the amount of read data requested during the same burst tenure). Therefore, each read request is monitored, instead of each DWORD transferred, during that read request tenure. This occurs because the read buffer always stores an entire cache line of read data from SDRAM, independent of the number of DWORDs requested during the read request. A read request of two, three, or four DWORDs that hit within the read buffer are counted by the performance monitors as only one hit to the read buffer because the read buffer always maintains an entire cache line of data, and a hit of one DWORD during a read burst request is guaranteed to hit the remaining data in that cache line during that same bus tenure. This occurs instead of unfairly counting four read buffer hits during a burst offour DWORDs requested because the entire cache line would result in a hit. Four independent read requests of one DWORD each result in four independent read buffer hits by the performance monitor because each read transfer is an individual read request. A ratio of read buffer HIT/MISS is provided by the performance monitors.
PC74HCT158D PC74HCT158D PC74HCT158D Price