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PC74HCT192P.652 PC74HCT192P.652 PC74HCT192P652 Datasheet

Parameter Description Conditions[5J Min Typ.[2] Max Unit
VDR Vcc for Data Retenbon 1.0 3.6 V
ICCDR Data Retention Current Vr:c = 1.OV CE > Vcc - 0.3V VIN > VCC - 0.3V or VIN < 0.3V No input may exceed Vcc+0.3V LL 0.5 7.5 oA
tCDR[3] Chip Deselect to Data Retention Time 0 ns
tR[4] Operation Recovery Time 70 ns


PC74HCT192P.652 PC74HCT192P.652 PC74HCT192P652 Price

70HF(R)
Parameters 10 t0 120 140 t0 160 Units
IF(AV, 70 70 A
@ Te 140 110 oc
IF(RMS, 1' O A
IFSM @50Hz 1200 A
@ 60Hz 1250 A
12t @50Hz 7100 A2S
@ 60Hz 6540 A2S
VRRM range 100 t0 1200 1400 t0 1600 V
Tj range - 65t0 180 - 65t0 150 oc


PC74HCT192P.652 PC74HCT192P.652 PC74HCT192P652 on stock
Conversion Length Conversion length (8-bit or 12-bit) is determined by the state of the Ao input, which is latched upon receipt of a conver- sion start transition (described below). IfAo is latched high, the conversion continues for 8 bits. The full 12-bit conver- sion will occur if Ao is low. If all 12 bits are read following an 8-bit conversion, the 3 LSBs (DBO-DB2) will be low (logic 0) and DB3 will be high (logic l). Ao is latched because it is also involved in enabling the output buffers. No other control inputs are latched.

AVCL =1 VOUT = 2Vp-p
fa=2 OMHz
2ND P ARMOF n r7
3RD -IAR¨0 NIC