| PARAMETER | TEST CONDITIONS | MIN TYP MAX | UNIT |
| VID(2) Differential input sensitivityt | | 150 1560 | mVp_p |
| tps Analog input intra-pair (+ to -) differential skew (see Note 6) | | 0.4 | tbit |
| Analog Input inter-pair or channel-to-channel skew tCcs (see Note 6) | | 1 | tpix§ |
| Worse case differential input clock jitter tolerancell tijit (see Note 6) | | 50 | ps |
| tfl Fall time of data and control signals#, lI | ST = Low, CL=5 pF ST = High, CL=10 pF | 2.4 1.9 | ns |
| trl Rise time of data and control signals#, lI | ST = Low, CL=5 pF ST = High, CL=10 pF | 2.4 1.9 | ns |
| tr2 Rise time of ODCK clock# | ST = Low, CL=5 pF ST = High, CL=10 pF | 2.4 1.9 | ns |
| tf2 Fall time of ODCK clock# | ST = Low, CL=5 pF ST = High, CL=10 pF | 2.4 1.9 | ns |
| Setup time, data and control signal to falling edge of ODCK tsul (OCK_INV = low)ll | ST = Low, CL=5 pF ST = High, CL=10 pF | 3 6 | ns |
| Hold time, data and control signal to falling edge of ODCK thl (OCK_INV = low)ll | ST = Low, CL=5 pF ST = High, CL=10 pF | 3 6 | ns |
| Setup time, data and control signal to rising edge of ODCK tsu2 (OCK_INV = high)ll | ST = Low, CL=5 pF ST = High, CL=10 pF | 3 6 | ns |
| Hold time, data and control signal to rising edge of ODCK th2 (OCK_INV = high)ll | ST = Low, CL=5 pF ST = High, CL=10 pF | 3 1 | ns |
| | PIX = Low (1-PIX/CLK) | 25 86 | |
| fODCK ODCK frequency | PIX = High (2-PIX/CLK) | 12 5 43 | MHz |
| ODCK duty-cycle | | 40% 50% 60% | |
| tpd(PDL) Propagation delay time from PD low to Hi-Z outputs | | 9 | ns |
| tpd(PDOL) Propagation delay time from PDO low to Hi-Z outputs | | 9 | ns |
| tt(HSC) Transition time between DE transition to SCDT low* | | 1e6 | tpix |
| tt(FSC) Transition time between DE transition to SCDT high* | | 1024 | tpix |
| td(st) Delay time, ODCK latching edge to QE[23:0] data output | STAG = Low Pixs = High | 0.25 | tpix |
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